公开(公告)号：US20110093829A1

公开(公告)日：2011-04-21

申请号：US12904409

申请日：2010-10-14

申请人： Takahiko Orita ,  Kazunori Kumagai ,  Yoshitaka Nishio ,  Ikuo Ohtsuka ,  Motoyuki Tanisho

发明人： Takahiko Orita ,  Kazunori Kumagai ,  Yoshitaka Nishio ,  Ikuo Ohtsuka ,  Motoyuki Tanisho

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  H05K3/0005

摘要： A non-transitory, computer-readable recording medium stores therein a design support program that causes a computer to execute selecting a wiring path whose line length is greatest among a plurality of wiring paths making up a wiring group leading from a transmission origin to a transmission destination; detecting insufficient line lengths of the wiring paths not selected, insufficiency being determined with respect to the line length of the selected wiring path; calculating the area of insufficiency according to a sum of the detected insufficient line lengths; allocating to a vicinity of the wiring group, a line length adjustment region corresponding to a sum of the areas of insufficiency calculated at calculating; and controlling a display screen to display the wiring group and the allocated line length adjustment region.

摘要翻译： 一种非暂时的计算机可读记录介质，其中存储有一个设计支持程序，使计算机执行选择构成从传输来源到传输的布线组的多个布线路径中线路长度最大的布线路径 目的地; 检测未选择的布线路径的线路长度不足，相对于所选择的布线路径的线路长度来确定不足; 根据检测到的不足线长度的总和计算不足的面积; 分配给布线组附近的线长度调整区域，与计算时计算出的功能不足区域的和相对应; 并且控制显示屏幕以显示配线组和所分配的线路长度调节区域。

公开(公告)号：US08443333B2

公开(公告)日：2013-05-14

申请号：US13044166

申请日：2011-03-09

申请人： Takahiko Orita ,  Kazunori Kumagai ,  Yoshitaka Nishio ,  Ikuo Ohtsuka ,  Motoyuki Tanisho

发明人： Takahiko Orita ,  Kazunori Kumagai ,  Yoshitaka Nishio ,  Ikuo Ohtsuka ,  Motoyuki Tanisho

IPC分类号： G06F15/04 ,  G06F17/50

CPC分类号： G06F17/5077

摘要： A non-transitory computer-readable recording medium storing a design supporting program causes a computer to perform: acquiring non-complying line lengths of a plurality of wiring paths; drawing for each of the wiring paths a wiring pattern connecting a transmission origin and a transmission destination based on a line length and a wiring route of the wiring path; and controlling the drawing to draw a line for each of the wiring paths, the line being divided into a first line amounting to a non-complying line length acquired at the acquiring and a second line being a wiring pass less the non-complying line length.

摘要翻译： 存储设计支持程序的非暂时计算机可读记录介质使计算机执行：获取多条布线路径的不符合线路长度; 基于布线路径的线路长度和布线路径，对每个布线路径绘制连接发送原点和发送目的地的布线图案; 并且控制绘图以为每个布线路径绘制一条线，将被划分为在采集时获取的不合格线长度的第一条线和第二条线的线作为不符合线路长度的布线通路 。

公开(公告)号：US08402414B2

公开(公告)日：2013-03-19

申请号：US13034135

申请日：2011-02-24

申请人： Motoyuki Tanisho ,  Toshiyasu Sakata ,  Yoshitaka Nishio ,  Ikuo Ohtsuka ,  Kazunori Kumagai

发明人： Motoyuki Tanisho ,  Toshiyasu Sakata ,  Yoshitaka Nishio ,  Ikuo Ohtsuka ,  Kazunori Kumagai

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A computer-readable, non-transitory medium stores therein a design support program that causes a computer executing tentative wiring processing between a first terminal group and a second terminal group in a tentative wiring area to execute a process. The process includes detecting unwired nets occurring in the tentative wiring area consequent to the tentative wiring processing; updating the tentative wiring area by expanding the tentative wiring area according to the number of unwired nets, if any unwired nets are detected at the detecting; controlling to execute the tentative wiring processing and the subsequent detecting with respect to the tentative wiring area updated at the updating; and determining the tentative wiring area to be a wiring area if no unwired nets are detected at the detecting.

摘要翻译： 计算机可读的非暂时性介质存储设计支持程序，使计算机在临时布线区域中的第一终端组和第二终端组之间执行临时布线处理，以执行处理。 该过程包括检测在临时布线处理之后的临时布线区域中发生的未梳棉网; 如果在检测中检测到任何未被感染的网络，则通过根据解开的网络的数量扩展临时布线区域来更新临时布线区域; 控制执行临时布线处理和相对于在更新时更新的暂定布线区域的后续检测; 以及如果在所述检测中没有检测到未被接收的网络，则将所述暂时布线区域确定为布线区域。

公开(公告)号：US08930869B2

公开(公告)日：2015-01-06

申请号：US13075632

申请日：2011-03-30

申请人： Ikuo Ohtsuka ,  Eiichi Konno ,  Takahiko Orita ,  Yoshitaka Nishio ,  Toshiyasu Sakata

发明人： Ikuo Ohtsuka ,  Eiichi Konno ,  Takahiko Orita ,  Yoshitaka Nishio ,  Toshiyasu Sakata

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A wiring-design aiding method for causing a computer to execute generating paths for buses so that the buses do not cross each other with respect to a wiring area including at least one wiring layer, the paths being represented by corresponding graphics The computer further executes verifying, for each bus, whether wires for nets belonging to the bus are successfully extracted from a component to which the bus is connected; and recording, in the wiring area, graphics representing the nets belonging to a bus for which it is determined in the verification that all the nets belonging to the bus are successfully extracted. The bus-path generation is re-executed with respect to the bus for which it is determined in the verification that at least one of the nets is not successfully extracted.

摘要翻译： 一种用于使计算机执行总线的产生路径的布线设计辅助方法，使得总线相对于包括至少一个布线层的布线区域彼此不相交，所述路径由相应的图形表示。 计算机还对每个总线进一步验证是否从总线连接的部件成功提取属于总线的网线; 并且在布线区域中记录表示属于总线的网络的图形，在该验证中确定属于总线的所有网络被成功提取。 相对于在验证中确定的总线，重新执行总线路径生成至少一个网络未成功提取。

公开(公告)号：US08402413B2

公开(公告)日：2013-03-19

申请号：US12721716

申请日：2010-03-11

申请人： Ikuo Ohtsuka ,  Takao Yamaguchi ,  Eiichi Konno ,  Toshiyasu Sakata ,  Takahiko Orita

发明人： Ikuo Ohtsuka ,  Takao Yamaguchi ,  Eiichi Konno ,  Toshiyasu Sakata ,  Takahiko Orita

IPC分类号： G06F17/50

CPC分类号： H05K3/0005 ,  G06F17/5077 ,  H05K2201/10734

摘要： A wiring design apparatus for designing a plurality of wiring lines of a printed circuit board including a plurality of connection posts arranged in a matrix, includes a processor, the processor providing an orthogonal grid including a plurality of rows and columns running over and between the connection posts, providing a plurality of diagonal paths each connecting at least one of the rows with at least one of the columns each running between each of adjacent pairs of the connection posts, and determining a route for each of the wiring lines by exclusively allocating to each of the wiring lines a selected part of the rows, the columns and the paths so that the selected part connects both ends of each of the wiring lines.

摘要翻译： 一种用于设计包括以矩阵形式布置的多个连接柱的印刷电路板的多条布线的布线设计装置，包括处理器，所述处理器提供正交网格，所述正交网格包括在所述连接之间和之间运行的多个行和列 柱，其提供多个对角线路径，每个对角线路径至少连接一条行，每条列中的至少一列在相邻的每对连接柱之间运行，并且通过专门地分配给每个布线来确定每个布线的路线 的布线选定部分的列，列和路径，使得所选择的部分连接每条布线的两端。

公开(公告)号：US08832630B2

公开(公告)日：2014-09-09

申请号：US13555245

申请日：2012-07-23

申请人： Ikuo Ohtsuka ,  Toshiyasu Sakata

发明人： Ikuo Ohtsuka ,  Toshiyasu Sakata

IPC分类号： G06F17/50 ,  H05K3/00

CPC分类号： G06F17/5077 ,  G06F17/5072 ,  G06F2217/40 ,  H05K3/0005

摘要： First and second pin groups are each formed from a plurality of pins associated with specific nets. Pins in the first pin group are to be wired to pins in the second pin group according to their associated nets. A candidate selection unit selects a set of pair candidates each specifying a first pair of pins in the first pin group and a second pair of pins in the second pin group. The first and second pairs of pins are associated with the same pair of nets, and their respective distances are within a specified range. A pair determination unit determines which pins in the first and second pin groups are to be wired in pairs, based on the pair candidates selected by the candidate selection unit.

摘要翻译： 第一和第二引脚组各自由与特定网络相关联的多个引脚形成。 第一个引脚组中的引脚将根据其相关的网络连接到第二个引脚组中的引脚。 候选选择单元选择一组配对候选，每组候选对象指定第一引脚组中的第一对引脚和第二引脚组中的第二对引脚。 第一和第二对引脚与同一对网络相关联，并且它们各自的距离在指定范围内。 对决定单元基于由候选选择单元选择的配对候选，确定第一和第二引脚组中哪些引脚成对布线。

公开(公告)号：US08762910B2

公开(公告)日：2014-06-24

申请号：US12579730

申请日：2009-10-15

申请人： Ikuo Ohtsuka

发明人： Ikuo Ohtsuka

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A wiring design method and apparatus are provided. The wiring design method includes dividing a wiring region represented by wiring region data to generate a plurality of first division regions based on a first wiring rule and generating, when a second wiring rule different from the first wiring rule may be set in the first division region, second division regions with the second wiring rule in the first division region.

摘要翻译： 提供了布线设计方法和装置。 布线设计方法包括：划分由布线区域数据表示的布线区域，以基于第一布线规则生成多个第一划分区域，并且当可以在第一划分区域中设置与第一布线规则不同的第二布线规则时， 在第一分割区域具有第二布线规则的第二分割区域。

公开(公告)号：US07765510B2

公开(公告)日：2010-07-27

申请号：US12068034

申请日：2008-01-31

申请人： Ikuo Ohtsuka

发明人： Ikuo Ohtsuka

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A wiring design device for an integrated circuit has been disclosed, which is capable of easily changing a via to a redundant via in a route for which search has been completed but which has been found to be changed after the design has advanced and of easily obtaining an optimum solution of a route even if the via is changed to the redundant via. The wiring design device for an integrated circuit comprises an evaluation value calculation circuit that calculates an evaluation value for each of a plurality of wiring routes from a start node to an end node, a determination circuit that determines a wiring route from the start node to the end node based on the calculated evaluation value, and a via type selection circuit that selects a via type to be used according to a difference between line widths of wires, wherein the evaluation value calculation circuit calculates, as to a wiring route in which a via is provided, the evaluation value after the via is provided by calculating a plurality of the evaluation values when different via types are used.

摘要翻译： 已经公开了一种用于集成电路的布线设计装置，其能够在已经完成搜索的路线中容易地将通道更改为冗余通道，但是在设计提前并且容易获得后已被发现被改变 即使通孔改变为冗余通道，路由的最佳解决方案。 用于集成电路的布线设计装置包括评估值计算电路，其计算从起始节点到结束节点的多条布线路线中的每一条路线的评估值，确定电路，确定从起始节点到 基于所计算的评估值的终端节点，以及根据导线的线宽之间的差选择要使用的通孔类型的通孔型选择电路，其中所述评估值计算电路针对其中通孔 通过在使用不同的通孔类型时，通过计算多个评价值来提供通孔之后的评价值。

公开(公告)号：US20080209384A1

公开(公告)日：2008-08-28

申请号：US12068034

申请日：2008-01-31

申请人： Ikuo Ohtsuka

发明人： Ikuo Ohtsuka

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A wiring design device for an integrated circuit has been disclosed, which is capable of easily changing a via to a redundant via in a route for which search has been completed but which has been found to be changed after the design has advanced and of easily obtaining an optimum solution of a route even if the via is changed to the redundant via. The wiring design device for an integrated circuit comprises an evaluation value calculation circuit that calculates an evaluation value for each of a plurality of wiring routes from a start node to an end node, a determination circuit that determines a wiring route from the start node to the end node based on the calculated evaluation value, and a via type selection circuit that selects a via type to be used according to a difference between line widths of wires, wherein the evaluation value calculation circuit calculates, as to a wiring route in which a via is provided, the evaluation value after the via is provided by calculating a plurality of the evaluation values when different via types are used.

摘要翻译： 已经公开了一种用于集成电路的布线设计装置，其能够在已经完成搜索的路线中容易地将通道更改为冗余通道，但是在设计提前并且容易获得后已被发现被改变 即使通孔改变为冗余通道，路由的最佳解决方案。 用于集成电路的布线设计装置包括评估值计算电路，其计算从起始节点到结束节点的多条布线路线中的每一条路线的评估值，确定电路，确定从起始节点到 基于所计算的评估值的终端节点，以及根据导线的线宽之间的差选择要使用的通孔类型的通孔型选择电路，其中所述评估值计算电路针对其中通孔 通过在使用不同的通孔类型时，通过计算多个评价值来提供通孔之后的评价值。