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    Field effect transistor
    3.
    发明授权
    Field effect transistor 有权
    场效应晶体管

    公开(公告)号：US08106382B2

    公开(公告)日：2012-01-31

    申请号：US12305824

    申请日：2007-06-18

    申请人： Tohru Saitoh ,  Takahiro Kawashima

    发明人： Tohru Saitoh ,  Takahiro Kawashima

    IPC分类号： H01L29/66

    CPC分类号： H01L29/78696 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/41733 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78654

    摘要： A source electrode 105 which is connected to a portion of at least one semiconductor nanostructure 103 among a plurality of semiconductor nanostructures, a drain electrode 106 connected to another portion of the semiconductor nanostructure 103, and a gate electrode 102 capable of controlling electrical conduction of the semiconductor nanostructure 103 are included. The semiconductor nanostructures 103 include a low concentration region 108 having a relatively low doping concentration and a pair of high concentration regions 107 having a higher doping concentration than that of the low concentration region 108 and being connected to both ends of the low concentration region 108. The doping concentration of the high concentration regions 107 is 1×1019 cm−3 or more; the length of the low concentration region 108 is shorter than a length of the gate electrode 102 along a direction from the source electrode 105 to the drain electrode 106; and the length of the gate electrode 102 is shorter than the interspace between the source electrode 105 and the drain electrode 106.

    摘要翻译： 连接到多个半导体纳米结构中的至少一个半导体纳米结构103的一部分的源电极105，连接到半导体纳米结构103的另一部分的漏电极106和能够控制半导体纳米结构103的导电的栅电极102 包括半导体纳米结构103。 半导体纳米结构103包括具有相对低的掺杂浓度的低浓度区域108和具有比低浓度区域108的掺杂浓度更高的掺杂浓度的一对高浓度区域107并且连接到低浓度区域108的两端。 高浓度区域107的掺杂浓度为1×1019cm-3以上; 低浓度区域108的长度比沿源极电极105至漏电极106的方向的栅电极102的长度短; 并且栅电极102的长度比源电极105和漏电极106之间的间隙短。

    Heterojunction biploar transistor and method for manufacturing same
    4.
    发明授权
    Heterojunction biploar transistor and method for manufacturing same 失效
    异质结双极晶体管及其制造方法

    公开(公告)号：US07719031B2

    公开(公告)日：2010-05-18

    申请号：US10564085

    申请日：2004-07-06

    申请人： Tohru Saitoh ,  Takahiro Kawashima ,  Ken Idota ,  Yoshihiko Kanzawa ,  Teruhito Ohnishi

    发明人： Tohru Saitoh ,  Takahiro Kawashima ,  Ken Idota ,  Yoshihiko Kanzawa ,  Teruhito Ohnishi

    IPC分类号： H01L29/74

    CPC分类号： H01L29/66242 ,  H01L29/7378

    摘要： A bipolar transistor 120 comprises a substrate 1, a intrinsic base region 11 and an extrinsic base region 12. The intrinsic base region 11 comprises a silicon buffer layer 109 comprised of silicon which is formed on the substrate 1, and a composition-ratio graded base layer 111 which is formed on the silicon buffer layer and comprises silicon and at least germanium and where a composition ratio of the germanium to the silicon varies in a thickness direction of the composition-ratio graded base layer 111. The extrinsic base region 12 comprises an extrinsic base formation layer 113 comprised of silicon which is formed on the substrate and adjacent to the silicon buffer layer. And the thickness of the extrinsic base formation layer 113 is not less than 40 nm.

    摘要翻译： 双极晶体管120包括衬底1，本征基极区域11和非本征基极区域12.本征基极区域11包括由衬底1上形成的硅构成的硅缓冲层109和组成比分级基底 层111，其形成在硅缓冲层上并且包含硅并且至少为锗，并且其中锗与硅的组成比在组成比梯度基底层111的厚度方向上变化。外部基极区12包括 外部基底形成层113由硅构成，其形成在衬底上并与硅缓冲层相邻。 外部基底形成层113的厚度不小于40nm。

    Vertical field effect transistor using linear structure as a channel region and method for fabricating the same
    8.
    发明授权
    Vertical field effect transistor using linear structure as a channel region and method for fabricating the same 有权
    使用线性结构作为沟道区域的垂直场效应晶体管及其制造方法

    公开(公告)号：US07586130B2

    公开(公告)日：2009-09-08

    申请号：US11344574

    申请日：2006-02-01

    申请人： Takahiro Kawashima ,  Tohru Saitoh ,  Takeshi Takagi

    发明人： Takahiro Kawashima ,  Tohru Saitoh ,  Takeshi Takagi

    IPC分类号： H01L29/732

    CPC分类号： H01L29/78696 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1606 ,  H01L29/42384 ,  H01L29/7781 ,  H01L29/78642 ,  Y10S977/938

    摘要： A vertical field effect transistor includes: an active region with a bundle of linear structures functioning as a channel region; a lower electrode, functioning as one of source and drain regions; an upper electrode, functioning as the other of the source and drain regions; a gate electrode for controlling the electric conductivity of at least a portion of the bundle of linear structures included in the active region; and a gate insulating film arranged between the active region and the gate electrode to electrically isolate the gate electrode from the bundle of linear structures. The transistor further includes a dielectric portion between the upper and lower electrodes. The upper electrode is located over the lower electrode with the dielectric portion interposed and includes an overhanging portion sticking out laterally from over the dielectric portion. The active region is located right under the overhanging portion of the upper electrode.

    摘要翻译： 垂直场效应晶体管包括：具有用作沟道区的线性结构束的有源区; 用作源极和漏极区之一的下电极; 上电极，用作源极和漏极区域中的另一个; 用于控制所述有源区域中包括的所述线性结构束的至少一部分的电导率的栅电极; 以及栅极绝缘膜，其布置在所述有源区和所述栅电极之间，以将所述栅电极与所述线结构的束电隔离。 晶体管还包括在上电极和下电极之间的电介质部分。 上电极位于下电极的上方，电介质部分插入，并且包括从电介质部分的上方横向突出的突出部分。 有源区域位于上电极的伸出部分正下方。

    Bipolar transistor and method for fabricating the same
    9.
    发明授权
    Bipolar transistor and method for fabricating the same 有权
    双极晶体管及其制造方法

    公开(公告)号：US07091099B2

    公开(公告)日：2006-08-15

    申请号：US10807307

    申请日：2004-03-24

    申请人： Teruhito Ohnishi ,  Koichiro Yuki ,  Tsuneichiro Sano ,  Tohru Saitoh ,  Ken Idota ,  Takahiro Kawashima ,  Shigeki Sawada

    发明人： Teruhito Ohnishi ,  Koichiro Yuki ,  Tsuneichiro Sano ,  Tohru Saitoh ,  Ken Idota ,  Takahiro Kawashima ,  Shigeki Sawada

    IPC分类号： H01L21/331

    CPC分类号： H01L29/66242 ,  H01L29/7378

    摘要： A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.

    摘要翻译： 双极晶体管包括形成在Si单晶层上的Si单结晶层，单晶Si / SiGeC层和多晶Si / SiGeC层，具有发射极开口部分的氧化膜，发射极 ，和发射极层。 在单晶Si / SiGeC层上形成本征基层，单晶Si / SiGeC层的一部分，多晶Si / SiGeC层和Co硅化物层一起形成外部基极层。 发射电极的厚度被设定为使得注入发射电极并在其中扩散的硼离子不会到达发射极 - 基极接合部分。