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    Semiconductor memory device and method of testing the same
    1.
    发明授权
    Semiconductor memory device and method of testing the same 有权
    半导体存储器件及其测试方法

    公开(公告)号：US07791967B2

    公开(公告)日：2010-09-07

    申请号：US11837722

    申请日：2007-08-13

    申请人： Takahiro Suzuki ,  Shinya Fujisawa ,  Tokumasa Hara

    发明人： Takahiro Suzuki ,  Shinya Fujisawa ,  Tokumasa Hara

    IPC分类号： G11C29/12

    CPC分类号： G11C29/14 ,  G11C16/04

    摘要： A semiconductor memory device includes a semiconductor memory, an auto-operation control circuit which outputs a clock signal, a sync read control circuit which outputs a sync read address in sync with the clock signal, a read control circuit which selects a read address of the semiconductor memory in accordance with an address of the sync read address, a read sense amplifier circuit which outputs a data read signal that is produced by sensing data that is read out of the semiconductor memory in accordance with the read address, and a determination circuit which compares the data read signal with an expectation value.

    摘要翻译： 半导体存储器件包括半导体存储器，输出时钟信号的自动操作控制电路，与时钟信号同步地输出同步读取地址的同步读取控制电路，选择读取地址的读取控制电路 半导体存储器，根据同步读取地址的地址，读出读出放大器电路，其输出通过根据读取的地址感测从半导体存储器读出的数据而产生的数据读取信号;以及确定电路， 将数据读取信号与期望值进行比较。

    MEMORY DEVICE AND BUILT IN SELF-TEST METHOD OF THE SAME
    2.
    发明申请
    MEMORY DEVICE AND BUILT IN SELF-TEST METHOD OF THE SAME 审中-公开
    存储器件并建立在其自检中的方法

    公开(公告)号：US20080282119A1

    公开(公告)日：2008-11-13

    申请号：US11877188

    申请日：2007-10-23

    申请人： Takahiro Suzuki ,  Shinya Fujisawa ,  Shoichiro Hashimoto ,  Tokumasa Hara

    发明人： Takahiro Suzuki ,  Shinya Fujisawa ,  Shoichiro Hashimoto ,  Tokumasa Hara

    IPC分类号： G11C29/12 ,  G06F11/27

    CPC分类号： G11C29/16

    摘要： A memory device including, a nonvolatile memory which stores a step item, a parameter start address, and a parameter which has an address corresponding to the parameter start address and defines the step item, and a controller which performs, on the nonvolatile memory, a test step corresponding to the step item defined by the parameter, the controller being formed in the same chip as the nonvolatile memory.

    摘要翻译： 一种存储装置，包括存储步骤项目的非易失性存储器，参数起始地址和具有与参数起始地址对应的地址并定义步骤项目的参数的参数，以及控制器，其在非易失性存储器上执行 测试步骤对应于由参数定义的步骤项目，控制器形成在与非易失性存储器相同的芯片中。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF TESTING THE SAME
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF TESTING THE SAME 有权
    半导体存储器件及其测试方法

    公开(公告)号：US20080043553A1

    公开(公告)日：2008-02-21

    申请号：US11837722

    申请日：2007-08-13

    申请人： Takahiro SUZUKI ,  Shinya Fujisawa ,  Tokumasa Hara

    发明人： Takahiro SUZUKI ,  Shinya Fujisawa ,  Tokumasa Hara

    IPC分类号： G11C7/00

    CPC分类号： G11C29/14 ,  G11C16/04

    摘要： A semiconductor memory device includes a semiconductor memory, an auto-operation control circuit which outputs a clock signal, a sync read control circuit which outputs a sync read address in sync with the clock signal, a read control circuit which selects a read address of the semiconductor memory in accordance with an address of the sync read address, a read sense amplifier circuit which outputs a data read signal that is produced by sensing data that is read out of the semiconductor memory in accordance with the read address, and a determination circuit which compares the data read signal with an expectation value.

    摘要翻译： 半导体存储器件包括半导体存储器，输出时钟信号的自动操作控制电路，与时钟信号同步地输出同步读取地址的同步读取控制电路，选择读取地址的读取控制电路 半导体存储器，根据同步读取地址的地址，读出读出放大器电路，其输出通过根据读取的地址感测从半导体存储器读出的数据而产生的数据读取信号;以及确定电路， 将数据读取信号与期望值进行比较。

    Semiconductor memory device which includes memory cell having charge accumulation layer and control gate
    4.
    发明授权
    Semiconductor memory device which includes memory cell having charge accumulation layer and control gate 有权
    半导体存储器件，其包括具有电荷累积层和控制栅极的存储单元

    公开(公告)号：US08082383B2

    公开(公告)日：2011-12-20

    申请号：US12018493

    申请日：2008-01-23

    申请人： Takahiro Suzuki ,  Shinya Fujisawa ,  Tokumasa Hara ,  Masuji Nishiyama

    发明人： Takahiro Suzuki ,  Shinya Fujisawa ,  Tokumasa Hara ,  Masuji Nishiyama

    IPC分类号： G06F13/00

    CPC分类号： G11C16/06

    摘要： A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

    摘要翻译： 半导体存储器件包括存储单元阵列，电源电路，读出放大器，控制电路和处理器。 存储单元阵列包括非易失性存储单元。 电源电路包括第一寄存器并产生电压。 读出放大器包括第二寄存器，从存储器单元读取并放大读取的数据。 控制电路包括第三寄存器并控制电源电路和读出放大器的操作。 处理器通过给第一至第三寄存器指令来控制电源电路，读出放大器和控制电路的操作。 控制电路解码在第三寄存器处接收的指令，以便基于解码结果来直接控制电源电路和读出放大器。

    Semiconductor memory device with memory cell including a charge storage layer and a control gate and method of controlling the same
    5.
    发明授权
    Semiconductor memory device with memory cell including a charge storage layer and a control gate and method of controlling the same 有权
    具有包括电荷存储层和控制栅的存储单元的半导体存储器件及其控制方法

    公开(公告)号：US07701781B2

    公开(公告)日：2010-04-20

    申请号：US12019245

    申请日：2008-01-24

    申请人： Shinya Fujisawa ,  Tokumasa Hara ,  Takahiro Suzuki

    发明人： Shinya Fujisawa ,  Tokumasa Hara ,  Takahiro Suzuki

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1045 ,  G11C7/22 ,  G11C16/26 ,  G11C2216/22

    摘要： A semiconductor memory device is capable of simultaneously carrying out a first operation and a second operation. The semiconductor memory device includes first and second control circuits, a select control circuit, and a select circuit. The first control circuit controls the first operation according to a first address signal and outputs a read start signal when the reading of the data is started. The second control circuit controls the second operation according to a second address signal and outputs a sequence flag when the first and second addresses coincide with each other. The select control circuit generates a select control signal. The select control signal is asserted if the second operation is carried out. The first control circuit instructs the select circuit to select the sequence flag if the select control signal is asserted or the data if the select control signal is negated.

    摘要翻译： 半导体存储器件能够同时执行第一操作和第二操作。 半导体存储器件包括第一和第二控制电路，选择控制电路和选择电路。 第一控制电路根据第一地址信号控制第一操作，并且当数据读取开始时输出读取开始信号。 第二控制电路根据第二地址信号控制第二操作，并且当第一和第二地址彼此一致时输出序列标志。 选择控制电路产生选择控制信号。 如果执行第二操作，则选择控制信号被置位。 如果选择控制信号被断言，则第一控制电路指示选择电路选择序列标志，或者如果选择控制信号被否定则指示数据。

    Semiconductor memory device which includes memory cell having charge accumulation layer and control gate
    6.
    发明授权
    Semiconductor memory device which includes memory cell having charge accumulation layer and control gate 有权
    半导体存储器件，其包括具有电荷累积层和控制栅极的存储单元

    公开(公告)号：US08219744B2

    公开(公告)日：2012-07-10

    申请号：US13301969

    申请日：2011-11-22

    申请人： Takahiro Suzuki ,  Shinya Fujisawa ,  Tokumasa Hara ,  Masuji Nishiyama

    发明人： Takahiro Suzuki ,  Shinya Fujisawa ,  Tokumasa Hara ,  Masuji Nishiyama

    IPC分类号： G06F12/02

    CPC分类号： G11C16/06

    摘要： A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

    摘要翻译： 半导体存储器件包括存储单元阵列，电源电路，读出放大器，控制电路和处理器。 存储单元阵列包括非易失性存储单元。 电源电路包括第一寄存器并产生电压。 读出放大器包括第二寄存器，从存储器单元读取并放大读取的数据。 控制电路包括第三寄存器并控制电源电路和读出放大器的操作。 处理器通过给第一至第三寄存器指令来控制电源电路，读出放大器和控制电路的操作。 控制电路解码在第三寄存器处接收的指令，以便基于解码结果来直接控制电源电路和读出放大器。

    SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE 有权
    半导体存储器件，其中包括具有充电累积层和控制栅的存储单元

    公开(公告)号：US20120063229A1

    公开(公告)日：2012-03-15

    申请号：US13301969

    申请日：2011-11-22

    申请人： Takahiro SUZUKI ,  Shinya Fujisawa ,  Tokumasa Hara ,  Masuji Nishiyama

    发明人： Takahiro SUZUKI ,  Shinya Fujisawa ,  Tokumasa Hara ,  Masuji Nishiyama

    IPC分类号： G11C16/26

    CPC分类号： G11C16/06

    摘要： A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

    摘要翻译： 半导体存储器件包括存储单元阵列，电源电路，读出放大器，控制电路和处理器。 存储单元阵列包括非易失性存储单元。 电源电路包括第一寄存器并产生电压。 读出放大器包括第二寄存器，从存储器单元读取并放大读取的数据。 控制电路包括第三寄存器并控制电源电路和读出放大器的操作。 处理器通过给第一至第三寄存器指令来控制电源电路，读出放大器和控制电路的操作。 控制电路解码在第三寄存器处接收的指令，以便基于解码结果来直接控制电源电路和读出放大器。

    SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELL INCLUDING A CHARGE STORAGE LAYER AND A CONTROL GATE AND METHOD OF CONTROLLING THE SAME
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELL INCLUDING A CHARGE STORAGE LAYER AND A CONTROL GATE AND METHOD OF CONTROLLING THE SAME 有权
    具有包含充电储存层的存储器单元的半导体存储器件和控制栅极及其控制方法

    公开(公告)号：US20080181022A1

    公开(公告)日：2008-07-31

    申请号：US12019245

    申请日：2008-01-24

    申请人： Shinya Fujisawa ,  Tokumasa Hara ,  Takahiro Suzuki

    发明人： Shinya Fujisawa ,  Tokumasa Hara ,  Takahiro Suzuki

    IPC分类号： G11C7/22

    CPC分类号： G11C7/1045 ,  G11C7/22 ,  G11C16/26 ,  G11C2216/22

    摘要： A semiconductor memory device is capable of simultaneously carrying out a first operation and a second operation. The semiconductor memory device includes first and second control circuits, a select control circuit, and a select circuit. The first control circuit controls the first operation according to a first address signal and outputs a read start signal when the reading of the data is started. The second control circuit controls the second operation according to a second address signal and outputs a sequence flag when the first and second addresses coincide with each other. The select control circuit generates a select control signal. The select control signal is asserted if the second operation is carried out. The first control circuit instructs the select circuit to select the sequence flag if the select control signal is asserted or the data if the select control signal is negated.

    摘要翻译： 半导体存储器件能够同时执行第一操作和第二操作。 半导体存储器件包括第一和第二控制电路，选择控制电路和选择电路。 第一控制电路根据第一地址信号控制第一操作，并且当数据读取开始时输出读取开始信号。 第二控制电路根据第二地址信号控制第二操作，并且当第一和第二地址彼此一致时输出序列标志。 选择控制电路产生选择控制信号。 如果执行第二操作，则选择控制信号被置位。 如果选择控制信号被断言，则第一控制电路指示选择电路选择序列标志，或者如果选择控制信号被否定则指示数据。