公开(公告)号：US07109558B2

公开(公告)日：2006-09-19

申请号：US10160098

申请日：2002-06-04

申请人： Takashi Nakano ,  Satoshi Shiraki ,  Yutaka Fukuda ,  Nobumasa Ueda ,  Shoji Miura

发明人： Takashi Nakano ,  Satoshi Shiraki ,  Yutaka Fukuda ,  Nobumasa Ueda ,  Shoji Miura

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7811 ,  H01L23/4824 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/7835 ,  Y10S257/901

摘要： A power MOS transistor formed of an array of source cells and drain cells on an IC chip substrate has a plurality of substrate contact cells, each formed external to the source cells, having respective substrate potential-setting electrodes to which an externally supplied substrate bias voltage can be applied, enabling the substrate potential to be set independently of the source potential of the transistor. It thereby becomes possible to modify the threshold voltage of the transistor or maintain a constant potential difference between the substrate potential and that of a gate input signal. Since the requirement for a substrate contact region within each source cell is eliminated, and the number of substrate contact cells can be fewer than that of the source cells, the chip area occupied by the transistor can be reduced by comparison with a prior art configuration providing such a substrate potential control capability.

公开(公告)号：US06274452B1

公开(公告)日：2001-08-14

申请号：US08965030

申请日：1997-11-05

申请人： Shoji Miura ,  Satoshi Shiraki ,  Hajime Soga

发明人： Shoji Miura ,  Satoshi Shiraki ,  Hajime Soga

IPC分类号： H01L2120

CPC分类号： H01L28/20 ,  H01L21/84 ,  H01L27/13 ,  H01L2924/0002 ,  H01L2924/00

摘要： After an insulating layer made of BPSG is formed on a diffusion layer, a contact hole is formed to expose the diffusion layer. Then, a first aluminum layer is formed in the contact hole. Then, first and second TEOS layers are formed. Thereafter, a thin film resistor is formed on the second TEOS layer by photo-lithography and etching treatments. In this process, the other parts are covered with the second TEOS layer to prevent being damaged. As a result, occurrence of a leak current at the diffusion layer and the like can be prevented. Further, a third TEOS layer is formed on the thin film resistor, and then a second aluminum layer is formed to be electrically connected to the thin film resistor through a contact hole by an ECR dry etching treatment. In this etching treatment, the thin film resistor is not damaged due to the third TEOS layer.

摘要翻译： 在扩散层上形成由BPSG制成的绝缘层之后，形成接触孔以露出扩散层。 然后，在接触孔中形成第一铝层。 然后，形成第一和第二TEOS层。 此后，通过光刻和蚀刻处理在第二TEOS层上形成薄膜电阻器。 在此过程中，其他部分被第二个TEOS层覆盖，以防止损坏。 结果，可以防止在扩散层等处发生泄漏电流。 此外，在薄膜电阻器上形成第三TEOS层，然后通过ECR干蚀刻处理通过接触孔形成第二铝层与薄膜电阻器电连接。 在这种蚀刻处理中，由于第三TEOS层，薄膜电阻器不会被损坏。

公开(公告)号：US06242792B1

公开(公告)日：2001-06-05

申请号：US09315132

申请日：1999-05-20

申请人： Shoji Miura ,  Satoshi Shiraki ,  Tetsuaki Kamiya ,  Makio Iida

发明人： Shoji Miura ,  Satoshi Shiraki ,  Tetsuaki Kamiya ,  Makio Iida

IPC分类号： H01L2941

CPC分类号： H01L28/20 ,  H01L22/22 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A laser trimming is favorably performed by a strengthened laser beam energy. A level difference portion having a taper portion that is oblique with respect to the thicknesswise direction of a semiconductor substrate is formed at a surface of a semiconductor substrate. An insulating film is formed thereon and has its surface made flat, and then the thin film element is formed thereon. Thereafter, laser trimming is performed with respect to the thin film resistor. As a result, a state of interference between incident laser beam and reflected laser beam reflected from the interface between the semiconductor substrate and the insulating film is varied to thereby enable the production of a zone where laser beam energy is strengthened and a zone where laser beam energy is weakened.

摘要翻译： 通过强化的激光束能量有利地进行激光修整。 在半导体基板的表面形成有具有相对于半导体基板的厚度方向倾斜的锥形部的电平差部。 在其上形成绝缘膜并使其表面平坦化，然后在其上形成薄膜元件。 此后，相对于薄膜电阻器进行激光微调。 结果，入射激光束与从半导体衬底和绝缘膜之间的界面反射的反射激光束之间的干涉状态变化，从而能够生成激光束能量增强的区域和激光束 能量减弱。

公开(公告)号：US20100176480A1

公开(公告)日：2010-07-15

申请号：US12654707

申请日：2009-12-29

申请人： Kouji Senda ,  Satoshi Shiraki ,  Yukihiro Maeda ,  Shinichi Hirose ,  Tetsuo Fujii ,  Takashi Nakano

发明人： Kouji Senda ,  Satoshi Shiraki ,  Yukihiro Maeda ,  Shinichi Hirose ,  Tetsuo Fujii ,  Takashi Nakano

IPC分类号： H01L27/06 ,  H01L21/78

CPC分类号： H01L21/84 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49551 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for manufacturing a semiconductor device includes: preparing a wafer formed of a SOI substrate; forming a circuit portion in a principal surface portion; removing a support substrate of the SOI substrate; fixing an insulation member on a backside of a semiconductor layer so as to be opposite to the circuit portion; dicing the wafer and dividing the wafer into multiple chips; arranging a first conductive member on the insulation member so as to be opposite to a part of the low potential reference circuit, and arranging a second conductive member on the insulation member so as to be opposite to a part of the high potential reference circuit; and coupling the first conductive member with a first part of the low potential reference circuit, and coupling the second conductive member with a second part of the high potential reference circuit.

摘要翻译： 一种制造半导体器件的方法包括：制备由SOI衬底形成的晶片; 在主表面部分形成电路部分; 去除SOI衬底的支撑衬底; 将绝缘构件固定在半导体层的背面以与电路部分相对; 切割晶片并将晶片分成多个芯片; 在所述绝缘构件上设置与所述低电位基准电路的一部分相对的第一导电构件，并且在所述绝缘构件上配置与所述高电位基准电路的一部分相反的第二导电构件; 以及将所述第一导电构件与所述低电位参考电路的第一部分耦合，以及将所述第二导电构件与所述高电位参考电路的第二部分耦合。

公开(公告)号：US20050001265A1

公开(公告)日：2005-01-06

申请号：US10864518

申请日：2004-06-10

申请人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

发明人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L21/763 ,  H01L21/8234 ,  H01L27/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/7824 ,  H01L21/26586 ,  H01L21/76286 ,  H01L21/763 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/0696 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/7835

摘要： A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.

摘要翻译： 半导体器件包括：具有主平面的半导体衬底; 设置在主平面上的基部区域; 源区域，其设置在所述基底区域中的所述主平面上，以比所述基底区域浅; 漏极区域，设置在所述主平面上，并且与所述基极区域间隔开; 设在主平面上的沟槽; 通过沟槽栅极绝缘膜设置在沟槽中的沟槽栅电极; 通过平面栅极绝缘膜设置在半导体衬底的主平面上的平面栅电极; 以及杂质扩散区域，其具有高浓度的杂质，并且设置在基极区域的一部分中，作为面向平面栅电极的沟道区域。

公开(公告)号：US07799667B2

公开(公告)日：2010-09-21

申请号：US12219008

申请日：2008-07-15

申请人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

发明人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

IPC分类号： H01L21/336

CPC分类号： H01L29/7824 ,  H01L21/26586 ,  H01L21/76286 ,  H01L21/763 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/0696 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/7835

摘要： A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.

摘要翻译： 半导体器件包括：具有主平面的半导体衬底; 设置在主平面上的基部区域; 源区域，其设置在所述基底区域中的所述主平面上，以比所述基底区域浅; 漏极区域，设置在所述主平面上，并且与所述基极区域间隔开; 设在主平面上的沟槽; 通过沟槽栅极绝缘膜设置在沟槽中的沟槽栅电极; 通过平面栅极绝缘膜设置在半导体衬底的主平面上的平面栅电极; 以及杂质扩散区域，其具有高浓度的杂质，并且设置在基极区域的一部分中，作为面向平面栅电极的沟道区域。

公开(公告)号：US08148809B2

公开(公告)日：2012-04-03

申请号：US12654707

申请日：2009-12-29

申请人： Kouji Senda ,  Satoshi Shiraki ,  Yukihiro Maeda ,  Shinichi Hirose ,  Tetsuo Fujii ,  Takashi Nakano

发明人： Kouji Senda ,  Satoshi Shiraki ,  Yukihiro Maeda ,  Shinichi Hirose ,  Tetsuo Fujii ,  Takashi Nakano

IPC分类号： H01L23/48

CPC分类号： H01L21/84 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49551 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for manufacturing a semiconductor device includes: preparing a wafer formed of a SOI substrate; forming a circuit portion in a principal surface portion; removing a support substrate of the SOI substrate; fixing an insulation member on a backside of a semiconductor layer so as to be opposite to the circuit portion; dicing the wafer and dividing the wafer into multiple chips; arranging a first conductive member on the insulation member so as to be opposite to a part of the low potential reference circuit, and arranging a second conductive member on the insulation member so as to be opposite to a part of the high potential reference circuit; and coupling the first conductive member with a first part of the low potential reference circuit, and coupling the second conductive member with a second part of the high potential reference circuit.

摘要翻译： 一种制造半导体器件的方法包括：制备由SOI衬底形成的晶片; 在主表面部分形成电路部分; 去除SOI衬底的支撑衬底; 将绝缘构件固定在半导体层的背面以与电路部分相对; 切割晶片并将晶片分成多个芯片; 在所述绝缘构件上设置与所述低电位基准电路的一部分相对的第一导电构件，并且在所述绝缘构件上配置与所述高电位基准电路的一部分相反的第二导电构件; 以及将所述第一导电构件与所述低电位参考电路的第一部分耦合，以及将所述第二导电构件与所述高电位参考电路的第二部分耦合。

公开(公告)号：US20080293202A1

公开(公告)日：2008-11-27

申请号：US12219008

申请日：2008-07-15

申请人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

发明人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

IPC分类号： H01L21/336

CPC分类号： H01L29/7824 ,  H01L21/26586 ,  H01L21/76286 ,  H01L21/763 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/0696 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/7835

摘要： A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.

摘要翻译： 半导体器件包括：具有主平面的半导体衬底; 设置在主平面上的基部区域; 源区域，其设置在所述基底区域中的所述主平面上，以比所述基底区域浅; 漏极区域，设置在所述主平面上，并且与所述基极区域间隔开; 设在主平面上的沟槽; 通过沟槽栅极绝缘膜设置在沟槽中的沟槽栅电极; 通过平面栅极绝缘膜设置在半导体衬底的主平面上的平面栅电极; 以及杂质扩散区域，其具有高浓度的杂质，并且设置在基极区域的一部分中，作为面向平面栅电极的沟道区域。

公开(公告)号：US09240445B2

公开(公告)日：2016-01-19

申请号：US14113419

申请日：2012-05-10

申请人： Takashi Suzuki ,  Norihito Tokura ,  Satoshi Shiraki ,  Shigeki Takahashi ,  Youichi Ashida ,  Akira Yamada

发明人： Takashi Suzuki ,  Norihito Tokura ,  Satoshi Shiraki ,  Shigeki Takahashi ,  Youichi Ashida ,  Akira Yamada

IPC分类号： H01L23/62 ,  H01L29/06 ,  H01L29/40 ,  H01L29/861

CPC分类号： H01L29/063 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/404 ,  H01L29/405 ,  H01L29/861

摘要： A lateral semiconductor device includes a semiconductor layer, an insulating layer, and a resistive field plate. The semiconductor layer includes a first semiconductor region and a second semiconductor region at a surface portion, and the second semiconductor region makes a circuit around the first semiconductor region. The insulating layer is formed on a surface of the semiconductor layer and is disposed between the first and second semiconductor regions. The resistive field plate is formed on a surface of the insulating layer. Between the first and second semiconductor regions, a first section and a second section are adjacent to each other along a circumferential direction around the first semiconductor region. The resistive field plate includes first and second resistive field plate sections respectively formed in the first and second sections, and the first and second resistive field plate sections are separated from each other.

摘要翻译： 横向半导体器件包括半导体层，绝缘层和电阻场板。 半导体层包括在表面部分处的第一半导体区域和第二半导体区域，并且第二半导体区域在第一半导体区域周围形成电路。 绝缘层形成在半导体层的表面上并且设置在第一和第二半导体区之间。 电阻场板形成在绝缘层的表面上。 在第一和第二半导体区域之间，第一部分和第二部分沿着围绕第一半导体区域的圆周方向彼此相邻。 电阻场板包括分别形成在第一和第二部分中的第一和第二电阻场板部分，并且第一和第二电阻场板部分彼此分离。

公开(公告)号：US20090152668A1

公开(公告)日：2009-06-18

申请号：US12314518

申请日：2008-12-11

申请人： Hiroki Sone ,  Akira Yamada ,  Satoshi Shiraki ,  Nozomu Akagi

发明人： Hiroki Sone ,  Akira Yamada ,  Satoshi Shiraki ,  Nozomu Akagi

IPC分类号： H01L25/16 ,  H01L23/495

CPC分类号： H01L27/1203 ,  H01L23/49589 ,  H01L23/585 ,  H01L24/48 ,  H01L27/092 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor apparatus is disclosed. The semiconductor apparatus includes an SOI substrate including an active layer, a buried insulation film and a support substrate; a low potential reference circuit part located in the active layer and operable at a first reference potential; a high potential reference circuit part located in the active layer and operable at a second reference potential; a level-shifting element forming part located in the active layer and for providing a level-shift between the first and second reference potentials; and an insulation member insulating first and second portions of the support substrate from each other, wherein locations of the first and second portions respectively correspond to the low and high potential reference circuit parts.

摘要翻译： 公开了一种半导体装置。 半导体装置包括：SOI基板，包括有源层，掩埋绝缘膜和支撑基板; 位于所述有源层中并且可在第一参考电位下操作的低电位参考电路部分; 位于所述有源层中并且可在第二参考电位下操作的高电位参考电路部分; 位于有源层中的电平移动元件形成部分，用于在第一和第二参考电位之间提供电平移位; 以及绝缘构件，其将所述支撑基板的第一和第二部分彼此绝缘，其中所述第一和第二部分的位置分别对应于所述低电位和高电位参考电路部分。