公开(公告)号：US07109558B2

公开(公告)日：2006-09-19

申请号：US10160098

申请日：2002-06-04

申请人： Takashi Nakano ,  Satoshi Shiraki ,  Yutaka Fukuda ,  Nobumasa Ueda ,  Shoji Miura

发明人： Takashi Nakano ,  Satoshi Shiraki ,  Yutaka Fukuda ,  Nobumasa Ueda ,  Shoji Miura

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7811 ,  H01L23/4824 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/7835 ,  Y10S257/901

摘要： A power MOS transistor formed of an array of source cells and drain cells on an IC chip substrate has a plurality of substrate contact cells, each formed external to the source cells, having respective substrate potential-setting electrodes to which an externally supplied substrate bias voltage can be applied, enabling the substrate potential to be set independently of the source potential of the transistor. It thereby becomes possible to modify the threshold voltage of the transistor or maintain a constant potential difference between the substrate potential and that of a gate input signal. Since the requirement for a substrate contact region within each source cell is eliminated, and the number of substrate contact cells can be fewer than that of the source cells, the chip area occupied by the transistor can be reduced by comparison with a prior art configuration providing such a substrate potential control capability.

公开(公告)号：US20100176480A1

公开(公告)日：2010-07-15

申请号：US12654707

申请日：2009-12-29

申请人： Kouji Senda ,  Satoshi Shiraki ,  Yukihiro Maeda ,  Shinichi Hirose ,  Tetsuo Fujii ,  Takashi Nakano

发明人： Kouji Senda ,  Satoshi Shiraki ,  Yukihiro Maeda ,  Shinichi Hirose ,  Tetsuo Fujii ,  Takashi Nakano

IPC分类号： H01L27/06 ,  H01L21/78

CPC分类号： H01L21/84 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49551 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for manufacturing a semiconductor device includes: preparing a wafer formed of a SOI substrate; forming a circuit portion in a principal surface portion; removing a support substrate of the SOI substrate; fixing an insulation member on a backside of a semiconductor layer so as to be opposite to the circuit portion; dicing the wafer and dividing the wafer into multiple chips; arranging a first conductive member on the insulation member so as to be opposite to a part of the low potential reference circuit, and arranging a second conductive member on the insulation member so as to be opposite to a part of the high potential reference circuit; and coupling the first conductive member with a first part of the low potential reference circuit, and coupling the second conductive member with a second part of the high potential reference circuit.

摘要翻译： 一种制造半导体器件的方法包括：制备由SOI衬底形成的晶片; 在主表面部分形成电路部分; 去除SOI衬底的支撑衬底; 将绝缘构件固定在半导体层的背面以与电路部分相对; 切割晶片并将晶片分成多个芯片; 在所述绝缘构件上设置与所述低电位基准电路的一部分相对的第一导电构件，并且在所述绝缘构件上配置与所述高电位基准电路的一部分相反的第二导电构件; 以及将所述第一导电构件与所述低电位参考电路的第一部分耦合，以及将所述第二导电构件与所述高电位参考电路的第二部分耦合。

公开(公告)号：US20050001265A1

公开(公告)日：2005-01-06

申请号：US10864518

申请日：2004-06-10

申请人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

发明人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L21/763 ,  H01L21/8234 ,  H01L27/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/7824 ,  H01L21/26586 ,  H01L21/76286 ,  H01L21/763 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/0696 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/7835

摘要： A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.

摘要翻译： 半导体器件包括：具有主平面的半导体衬底; 设置在主平面上的基部区域; 源区域，其设置在所述基底区域中的所述主平面上，以比所述基底区域浅; 漏极区域，设置在所述主平面上，并且与所述基极区域间隔开; 设在主平面上的沟槽; 通过沟槽栅极绝缘膜设置在沟槽中的沟槽栅电极; 通过平面栅极绝缘膜设置在半导体衬底的主平面上的平面栅电极; 以及杂质扩散区域，其具有高浓度的杂质，并且设置在基极区域的一部分中，作为面向平面栅电极的沟道区域。

公开(公告)号：US08148809B2

公开(公告)日：2012-04-03

申请号：US12654707

申请日：2009-12-29

申请人： Kouji Senda ,  Satoshi Shiraki ,  Yukihiro Maeda ,  Shinichi Hirose ,  Tetsuo Fujii ,  Takashi Nakano

发明人： Kouji Senda ,  Satoshi Shiraki ,  Yukihiro Maeda ,  Shinichi Hirose ,  Tetsuo Fujii ,  Takashi Nakano

IPC分类号： H01L23/48

CPC分类号： H01L21/84 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49551 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for manufacturing a semiconductor device includes: preparing a wafer formed of a SOI substrate; forming a circuit portion in a principal surface portion; removing a support substrate of the SOI substrate; fixing an insulation member on a backside of a semiconductor layer so as to be opposite to the circuit portion; dicing the wafer and dividing the wafer into multiple chips; arranging a first conductive member on the insulation member so as to be opposite to a part of the low potential reference circuit, and arranging a second conductive member on the insulation member so as to be opposite to a part of the high potential reference circuit; and coupling the first conductive member with a first part of the low potential reference circuit, and coupling the second conductive member with a second part of the high potential reference circuit.

摘要翻译： 一种制造半导体器件的方法包括：制备由SOI衬底形成的晶片; 在主表面部分形成电路部分; 去除SOI衬底的支撑衬底; 将绝缘构件固定在半导体层的背面以与电路部分相对; 切割晶片并将晶片分成多个芯片; 在所述绝缘构件上设置与所述低电位基准电路的一部分相对的第一导电构件，并且在所述绝缘构件上配置与所述高电位基准电路的一部分相反的第二导电构件; 以及将所述第一导电构件与所述低电位参考电路的第一部分耦合，以及将所述第二导电构件与所述高电位参考电路的第二部分耦合。

公开(公告)号：US20080293202A1

公开(公告)日：2008-11-27

申请号：US12219008

申请日：2008-07-15

申请人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

发明人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

IPC分类号： H01L21/336

CPC分类号： H01L29/7824 ,  H01L21/26586 ,  H01L21/76286 ,  H01L21/763 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/0696 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/7835

摘要： A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.

摘要翻译： 半导体器件包括：具有主平面的半导体衬底; 设置在主平面上的基部区域; 源区域，其设置在所述基底区域中的所述主平面上，以比所述基底区域浅; 漏极区域，设置在所述主平面上，并且与所述基极区域间隔开; 设在主平面上的沟槽; 通过沟槽栅极绝缘膜设置在沟槽中的沟槽栅电极; 通过平面栅极绝缘膜设置在半导体衬底的主平面上的平面栅电极; 以及杂质扩散区域，其具有高浓度的杂质，并且设置在基极区域的一部分中，作为面向平面栅电极的沟道区域。

公开(公告)号：US07799667B2

公开(公告)日：2010-09-21

申请号：US12219008

申请日：2008-07-15

申请人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

发明人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

IPC分类号： H01L21/336

CPC分类号： H01L29/7824 ,  H01L21/26586 ,  H01L21/76286 ,  H01L21/763 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/0696 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/7835

摘要： A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.

摘要翻译： 半导体器件包括：具有主平面的半导体衬底; 设置在主平面上的基部区域; 源区域，其设置在所述基底区域中的所述主平面上，以比所述基底区域浅; 漏极区域，设置在所述主平面上，并且与所述基极区域间隔开; 设在主平面上的沟槽; 通过沟槽栅极绝缘膜设置在沟槽中的沟槽栅电极; 通过平面栅极绝缘膜设置在半导体衬底的主平面上的平面栅电极; 以及杂质扩散区域，其具有高浓度的杂质，并且设置在基极区域的一部分中，作为面向平面栅电极的沟道区域。

公开(公告)号：US08952083B2

公开(公告)日：2015-02-10

申请号：US13070572

申请日：2011-03-24

申请人： Takashi Nakano ,  Tomoyuki Fujita ,  Yoshitomi Morizawa

发明人： Takashi Nakano ,  Tomoyuki Fujita ,  Yoshitomi Morizawa

IPC分类号： C08K5/34 ,  C08F214/18 ,  C08F214/26 ,  C08J3/09 ,  C08J5/18 ,  C09D127/12 ,  C09D127/18 ,  C08K5/00

CPC分类号： C08F214/18 ,  C08F214/26 ,  C08F214/265 ,  C08J3/093 ,  C08J5/18 ,  C08J2327/18 ,  C08K5/0008 ,  C09D127/12 ,  C09D127/18

摘要： To provide a composition comprising a fluorocopolymer such as an ethylene/tetrafluoroethylene copolymer which can be produced at a relatively low temperature, and its production process.A fluorocopolymer composition which comprises a fluorocopolymer such as an ethylene/tetrafluoroethylene copolymer and a fluorinated aromatic compound having a melting point of at most 230° C. and having a fluorine content in the compound of from 5 to 75 mass %, and is in a solution state at a temperature of at most the melting point of the fluorocopolymer, and a process for producing the fluorocopolymer composition, which comprises a step of dissolving the fluorocopolymer in a solvent containing the fluorinated aromatic compound at a temperature of at most the melting point of the fluorocopolymer.

摘要翻译： 提供包含可在相对较低温度下生产的含氟共聚物如乙烯/四氟乙烯共聚物的组合物及其制备方法。 一种含氟共聚物组合物，其包含含氟共聚物如乙烯/四氟乙烯共聚物和熔点至多为230℃的氟化芳族化合物，化合物中的氟含量为5〜75质量％，为 在含氟共聚物的熔点以上的温度下的溶液状态，以及含氟共聚物组合物的制造方法，其特征在于，含有含氟共聚物在含氟化芳香族化合物的溶剂中的溶解温度为 含氟共聚物。

公开(公告)号：US08602654B2

公开(公告)日：2013-12-10

申请号：US12308555

申请日：2007-10-31

申请人： Takaaki Kaikogi ,  Kazuhiko Yamashita ,  Takashi Nakano ,  Yuichiro Waki ,  Motohisa Uesato ,  Yutaka Yamada

发明人： Takaaki Kaikogi ,  Kazuhiko Yamashita ,  Takashi Nakano ,  Yuichiro Waki ,  Motohisa Uesato ,  Yutaka Yamada

IPC分类号： F16C32/00

CPC分类号： G01K13/08 ,  F16C17/243

摘要： A bearing temperature monitoring device and bearing device provided with the monitoring device composed so that occurrence of scratch on the rotation shaft supported by the bearing caused by a bearing temperature carrying member integrated in the bearing such that its top end surface faces the rotation shaft, are provided. The bearing device is provided with a bearing temperature detecting device which comprises a bearing temperature carrying member made of material larger in thermal conductivity than the bearing layer and shaped to have a protruded part to be inserted slidably into a through hole in the bearing layer and a base part to be received in a cylindrical space in the back metal, the base part serving to restrict protrusion of the protruded part into the through hole so that the top end surface thereof is level with the sliding surface of the bearing layer, a pushing member attached to the back metal to push the temperature carrying member so that the member move toward the back metal against the pushing force of the pushing member when bearing load exerts on the temperature carrying member, and a temperature sensor for detecting temperature of the temperature carrying member.

摘要翻译： 一种轴承温度监测装置和轴承装置，其具有监测装置，其特征在于，由轴承温度承载部件一体地支承在轴承上的旋转轴上产生划痕，使其顶端面朝向旋转轴 提供。 轴承装置设置有轴承温度检测装置，该装置包括轴承温度承载部件，该轴承温度承载部件由比导热层更大导热性的材料制成，并且成形为具有可滑动地插入轴承层的通孔中的突出部分， 基部被容纳在后金属的圆筒形空间中，基部用于限制突出部突出到通孔中，使得其顶端面与轴承层的滑动面平齐，推动构件 附着在背金属上以推压承载构件，使得当轴承负载施加在承载温度承载构件上时，构件抵抗推动构件的推力移动，并且用于检测温度承载构件的温度的温度传感器 。

公开(公告)号：US20130053493A1

公开(公告)日：2013-02-28

申请号：US13613014

申请日：2012-09-13

申请人： Takashi Nakano ,  Kuniko Okano

发明人： Takashi Nakano ,  Kuniko Okano

IPC分类号： C09D127/18 ,  C08K5/101 ,  C08K5/07

CPC分类号： C08L23/08 ,  C08J3/005 ,  C08J2323/08 ,  C08J2327/18 ,  C08L27/06 ,  C08L27/08 ,  C08L27/12 ,  C08L27/16 ,  C08L27/18 ,  C09D123/0892 ,  C09D127/18 ,  C08L2666/02 ,  C08L23/10 ,  C08L33/08 ,  C08L33/10 ,  C08L33/12 ,  C08L31/04 ,  C08L51/00 ,  C08L71/12 ,  C08L67/02 ,  C08L77/00 ,  C08L25/06

摘要： This invention relates to a method for producing a fluorinated copolymer composition, capable of uniformly mixing a fluorinated copolymer (A) having repeating units derived from ethylene and repeating units derived from tetrafluoroethylene, and a thermoplastic resin (B), at a relatively low temperature. The invention also relates to a method for producing a fluorinated copolymer composition comprising a fluorinated copolymer (A), a thermoplastic resin (B) which excludes the fluorinated copolymer (A), and a medium (C) capable of dissolving at least the fluorinated copolymer (A). The invention also relates to a coating composition capable of forming a coating film provided with characteristics of the fluorinated copolymer (A) and the thermoplastic resin (B), an article having such a coating film, and a molded product.

摘要翻译： 本发明涉及在较低温度下均匀混合衍生自乙烯的重复单元的含氟共聚物（A）和衍生自四氟乙烯的重复单元和热塑性树脂（B））的含氟共聚物组合物的制造方法。 本发明还涉及一种含氟共聚物（A），不含氟化共聚物（A）的热塑性树脂（B））和至少能够溶解氟化共聚物的介质（C）的含氟共聚物组合物的制造方法 （一个）。 本发明还涉及能够形成具有含氟共聚物（A）和热塑性树脂（B）的特性的涂膜的涂料组合物，具有这种涂膜的制品和模塑产品。

公开(公告)号：US08375556B2

公开(公告)日：2013-02-19

申请号：US12762792

申请日：2010-04-19

申请人： Takashi Nakano

发明人： Takashi Nakano

IPC分类号： A63B53/00 ,  B26D3/06

CPC分类号： A63B53/04 ,  A63B53/047 ,  A63B53/0487 ,  A63B2053/0408 ,  A63B2053/0445 ,  A63B2209/00 ,  A63B2209/02 ,  B23C3/30 ,  B23C5/10 ,  B23C2200/203 ,  B23C2200/205 ,  B23C2265/08 ,  Y10T29/49995 ,  Y10T29/49996 ,  Y10T83/0304 ,  Y10T83/05 ,  Y10T83/0605

摘要： A manufacturing method of the present invention includes the steps of: preparing a pre-line forming member having no face line; and cutting the pre-line forming member using a cutter 12 to form the face line on the pre-line forming member. The cutter 8 has a tip part having a cutting surface. The cutting surface has a recessed curved surface c4. An edge of the face line 8 is cut by the recessed curved surface c4. Preferably, the step of cutting is carried out by axial rotation of the cutter 8. Preferably, the cutting surface has a plane part c5 formed on an upper side of the recessed curved surface c4. Preferably, the upper side plane part c5 is perpendicular to a rotation axis rz of the cutter 12. Preferably, the cutting surface has a conical surface Fc formed on a lower side of the recessed curved surface c4.

摘要翻译： 本发明的制造方法包括以下步骤：准备没有面线的预制线形成部件; 并使用切割器12切割预成型构件，以在预成型构件上形成面线。 切割器8具有具有切割表面的尖端部分。 切割表面具有凹入的曲面c4。 表面线8的边缘被凹入的曲面c4切割。 优选地，通过切割器8的轴向旋转来进行切割的步骤。优选地，切割表面具有形成在凹入曲面c4的上侧上的平面部分c5。 优选地，上侧平面部分c5垂直于切割器12的旋转轴线rz。优选地，切割表面具有形成在凹入曲面c4的下侧上的锥形表面Fc。