公开(公告)号：US20130049999A1

公开(公告)日：2013-02-28

申请号：US13338338

申请日：2011-12-28

申请人： TAKASHI OSHIMA ,  Taizo Yamawaki ,  Tomomi Takahashi

发明人： TAKASHI OSHIMA ,  Taizo Yamawaki ,  Tomomi Takahashi

IPC分类号： H03M1/10

CPC分类号： H03M1/1009 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/1028 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/804

摘要： A reference A/D conversion unit is connected in parallel to an input common to a time-interleaved A/D converter to be a calibration target, and the output of each unitary A/D conversion unit which makes up the time-interleaved A/D converter is calibrated in a digital region by using a low-speed high-resolution A/D conversion result output from the reference A/D conversion unit. Also, fCLK/N (fCLK represents an overall sampling rate of the time-interleaved A/D converter, and N is relatively prime to the number of unitary A/D conversion units connected in parallel M) is set as the operation clock frequency of the reference A/D conversion unit. Samplings of all unitary A/D conversion units can be sequentially synchronized with the sampling of the reference A/D conversion unit, and the operation clock frequency of the reference A/D converter can be made N times slower than the overall sampling rate of the time-interleaved A/D converter.

摘要翻译： 参考A / D转换单元并联连接到时间交织的A / D转换器的公共端作为校准对象，并且构成时间交织的A / D转换单元的每个单位A / D转换单元的输出， D转换器通过使用从参考A / D转换单元输出的低速高分辨率A / D转换结果在数字区域进行校准。 另外，fCLK / N（fCLK表示时间交织的A / D转换器的总体采样率，N是并行连接的单位A / D转换单元的数量的N相对于M）被设定为操作时钟频率 参考A / D转换单元。 所有单位A / D转换单元的采样可以与参考A / D转换单元的采样顺序同步，并且参考A / D转换器的工作时钟频率可以比总的采样率慢 时间交织的A / D转换器。

公开(公告)号：US20090017776A1

公开(公告)日：2009-01-15

申请号：US12169756

申请日：2008-07-09

申请人： TAKASHI OSHIMA ,  Taizo Yamawaki

发明人： TAKASHI OSHIMA ,  Taizo Yamawaki

IPC分类号： H04B1/38 ,  H04B17/00

CPC分类号： H04B1/0039

摘要： Conventional digital calibration type analog-to-digital converters cannot converge calibration within an preamble period of a packet signal. An analog-to-digital converter is subjected to digital calibration using a beacon signal, a polling signal, or another user signal or a signal applied from a transceiver side to a receiver side. Some or all of circuits are brought into a sleep mode in a period except data reception and the analog-to-digital converter calibration such that a signal monitor unit detects another signal to activate the circuit in the sleep mode for performing the calibration of the analog-to-digital converter for reducing the power consumption.

摘要翻译： 传统的数字校准型模数转换器不能在分组信号的前同步码周期内收敛校准。 使用信标信号，轮询信号或另一用户信号或从收发机侧向接收机侧施加的信号对模数转换器进行数字校准。 部分或全部电路在除了数据接收和模数转换器校准之外的周期中进入休眠模式，使得信号监视单元检测到另一个信号，以在休眠模式下激活电路，以执行模拟 数字转换器，用于降低功耗。

公开(公告)号：US08169350B2

公开(公告)日：2012-05-01

申请号：US12273240

申请日：2008-11-18

申请人： Takashi Oshima ,  Taizo Yamawaki

发明人： Takashi Oshima ,  Taizo Yamawaki

IPC分类号： H03M1/10 ,  H04B1/12 ,  H04B1/18

CPC分类号： H03M1/122 ,  H03M1/1033 ,  H03M1/167

摘要： A wireless receiving circuit having an analog-digital converter of digital calibration type constituted by plural analog-digital converter units, shares portions about digital calibration, and applies the result of calibration of one analog-digital converter unit to other analog-digital converter units to appropriately perform each digital calibration of the plural analog-digital converter units. For example, in a wireless receiving circuit having an analog-digital converter of digital calibration type constituted of an analog-digital converter unit of I side and an analog-digital converter unit of Q side, portions about digital calibration are shared, and a calibration result of I side is applied to Q side.

摘要翻译： 一种无线接收电路，具有由多个模拟数字转换器单元构成的具有数字校准类型的模拟数字转换器，共享关于数字校准的部分，并将一个模拟数字转换器单元的校准结果应用于其它模数转换器单元， 适当地执行多个模拟数字转换器单元的每个数字校准。 例如，在具有由I侧的模拟数字转换器单元和Q侧的模拟数字转换器单元构成的数字校准类型的模拟数字转换器的无线接收电路中，共享关于数字校准的部分，并且校准 我方的结果适用于Q方。

公开(公告)号：US08004445B2

公开(公告)日：2011-08-23

申请号：US12720669

申请日：2010-03-10

申请人： Takashi Oshima ,  Taizo Yamawaki

发明人： Takashi Oshima ,  Taizo Yamawaki

IPC分类号： H03M1/34

CPC分类号： H03M1/1004 ,  H03M1/002 ,  H03M1/005 ,  H03M1/1009 ,  H03M1/126 ,  H03M1/44

摘要： In a wireless chip receiving the multi-rate data according to the related art, power consumption and a circuit area of an analog-to-digital converter become large. In a digital calibration type analog-to-digital converter including both a reference analog-to-digital conversion unit and a main analog-to-digital conversion unit, when processing the high-sample rate wireless receive signal, both the reference analog-to-digital conversion unit and the main analog-to-digital conversion unit are operated to configure a general digital calibration type analog-to-digital converter, and when processing a low-sample rate wireless receive signal, analog-to-digital conversion is performed by using the reference analog-to-digital conversion unit and operations of the main analog-to-digital conversion unit or the like are stopped to remarkably reduce power consumption.

摘要翻译： 在接收根据现有技术的多速率数据的无线芯片中，功率消耗和模数转换器的电路面积变大。 在包括参考模数转换单元和主模数转换单元的数字校准类型模数转换器中，当处理高抽样率无线接收信号时，参考模拟到数字转换单元 操作数字转换单元和主模拟 - 数字转换单元来配置通用数字校准类型模数转换器，并且当处理低采样率无线接收信号时，执行模拟 - 数字转换 通过使用参考模数转换单元，并且停止主模数转换单元等的操作以显着地降低功耗。

公开(公告)号：US20090011728A1

公开(公告)日：2009-01-08

申请号：US12216092

申请日：2008-06-30

申请人： Takashi Kawamoto ,  Takashi Oshima ,  Taizo Yamawaki ,  Manabu Nakamura

发明人： Takashi Kawamoto ,  Takashi Oshima ,  Taizo Yamawaki ,  Manabu Nakamura

IPC分类号： H03F1/02 ,  H04B1/04

CPC分类号： H03F1/0227 ,  H03F1/0205 ,  H03F1/32 ,  H03F3/24 ,  H03F2200/102 ,  H03F2200/99

摘要： A DCDC converter includes a signal splitting unit that splits an input signal into N signal components; N DCDC converter elements that process individually the N split signals; and an adder that adds outputs from the plural DCDC converter elements to generate output signals. Each of the DCDC converter elements has an operation band narrower than an applicable frequency band of the input signal, and selects a design parameter that allows a conversion efficiency of the DCDC converter elements to be optimized for any band of the applicable frequency bands. For example, the parameter of a PMOS transistor and a NMOS transistor, which configure an inverter is designed to optimize the efficiency at any of frequency bands. The frequency band of the input signal is split, and each of the split outputs is input to a DCDC converter element that has a corresponding frequency and high efficiency characteristic.

摘要翻译： DCDC转换器包括将输入信号分解为N个信号分量的信号分离单元; N个DCDC转换器元件，分别处理N个分离信号; 以及加法器，其添加来自多个DCDC转换器元件的输出以产生输出信号。 每个DCDC转换器元件具有比输入信号的适用频带窄的操作频带，并且选择允许DCDC转换器元件的转换效率针对适用频带的任何频带进行优化的设计参数。 例如，配置反相器的PMOS晶体管和NMOS晶体管的参数被设计为优化任何频带处的效率。 输入信号的频带被分离，并且每个分离输出被输入到具有对应的频率和高效率特性的DCDC转换器元件。

公开(公告)号：US08102289B2

公开(公告)日：2012-01-24

申请号：US12676357

申请日：2009-02-19

申请人： Takashi Oshima ,  Taizo Yamawaki ,  Tomomi Takahashi

发明人： Takashi Oshima ,  Taizo Yamawaki ,  Tomomi Takahashi

IPC分类号： H03M1/10

CPC分类号： H03M1/1009 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/1028 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/804

摘要： In the digital calibration technique of the conventional time-interleaved analog/digital converter, it is impossible to perform highly-accurate calibration that supports a high-speed sampling rate of the next-generation application and achieves a high resolution. For its solution, a reference A/D conversion unit is connected in parallel to an input common to a time-interleaved A/D converter to be a calibration target, and the output of each unitary A/D conversion unit which makes up the time-interleaved A/D converter is calibrated in a digital region by using a low-speed high-resolution A/D conversion result output from the reference A/D conversion unit. Also, fCLK/N (fCLK represents an overall sampling rate of the time-interleaved A/D converter, and N is relatively prime to the number of unitary A/D conversion units connected in parallel M) is set as the operation clock frequency of the reference A/D conversion unit. In this configuration, samplings of all unitary A/D conversion units can be sequentially synchronized with the sampling of the reference A/D conversion unit, and the operation clock frequency of the reference A/D converter can be made N times slower than the overall sampling rate of the time-interleaved A/D converter.

摘要翻译： 在传统的时间交错模拟/数字转换器的数字校准技术中，不可能执行支持下一代应用的高速采样率的高精度校准，并实现高分辨率。 对于其解决方案，参考A / D转换单元并联连接到时间交织的A / D转换器的公共端作为校准目标，并且构成时间的每个单位A / D转换单元的输出 通过使用从参考A / D转换单元输出的低速高分辨率A / D转换结果，在数字区域校准交错A / D转换器。 另外，fCLK / N（fCLK表示时间交织的A / D转换器的总体采样率，N是并行连接的单位A / D转换单元的数量的N相对于M）被设定为操作时钟频率 参考A / D转换单元。 在这种配置中，所有单位A / D转换单元的采样可以与参考A / D转换单元的采样顺序同步，并且参考A / D转换器的操作时钟频率可以比总体的N倍慢 时间交织A / D转换器的采样率。

公开(公告)号：US20110128171A1

公开(公告)日：2011-06-02

申请号：US12676357

申请日：2009-02-19

申请人： Takashi Oshima ,  Taizo Yamawaki ,  Tomomi Takahashi

发明人： Takashi Oshima ,  Taizo Yamawaki ,  Tomomi Takahashi

IPC分类号： H03M1/10

CPC分类号： H03M1/1009 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/1028 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/804

摘要： In the digital calibration technique of the conventional time-interleaved analog/digital converter, it is impossible to perform highly-accurate calibration that supports a high-speed sampling rate of the next-generation application and achieves a high resolution. For its solution, a reference A/D conversion unit is connected in parallel to an input common to a time-interleaved A/D converter to be a calibration target, and the output of each unitary A/D conversion unit which makes up the time-interleaved A/D converter is calibrated in a digital region by using a low-speed high-resolution A/D conversion result output from the reference A/D conversion unit. Also, fCLK/N (fCLK represents an overall sampling rate of the time-interleaved A/D converter, and N is relatively prime to the number of unitary A/D conversion units connected in parallel M) is set as the operation clock frequency of the reference A/D conversion unit. In this configuration, samplings of all unitary A/D conversion units can be sequentially synchronized with the sampling of the reference A/D conversion unit, and the operation clock frequency of the reference A/D converter can be made N times slower than the overall sampling rate of the time-interleaved A/D converter.

摘要翻译： 在传统的时间交错模拟/数字转换器的数字校准技术中，不可能执行支持下一代应用的高速采样率的高精度校准，并实现高分辨率。 对于其解决方案，参考A / D转换单元并联连接到时间交织的A / D转换器的公共端作为校准目标，并且构成时间的每个单位A / D转换单元的输出 通过使用从参考A / D转换单元输出的低速高分辨率A / D转换结果，在数字区域校准交错A / D转换器。 另外，fCLK / N（fCLK表示时间交织的A / D转换器的总体采样率，N是并行连接的单位A / D转换单元的数量的N相对于M）被设定为操作时钟频率 参考A / D转换单元。 在这种配置中，所有单一A / D转换单元的采样可以与参考A / D转换单元的采样顺序同步，并且参考A / D转换器的操作时钟频率可以比总体的N倍慢 时间交织A / D转换器的采样率。

公开(公告)号：US07843369B2

公开(公告)日：2010-11-30

申请号：US12270212

申请日：2008-11-13

申请人： Tomomi Takahashi ,  Takashi Oshima ,  Taizo Yamawaki

发明人： Tomomi Takahashi ,  Takashi Oshima ,  Taizo Yamawaki

IPC分类号： H03M1/10

CPC分类号： H03M1/1033 ,  H03M1/12

摘要： In a wireless transmitter and receiver, a background calibration type analog-to-digital converter generally occupies a large area because of the phase compensating capacity of an op-amp included in a reference analog-to-digital conversion unit. Further, the calibration type analog-to-digital converter generally requires a sample and hold circuit to exclude influence of parasitic capacitance of wirings, thereby increasing power consumption. Digital calibration is performed by using, as a signal for calibration, an input signal of a digital-to-analog converter in a transmitter circuit of the wireless transmitter and receiver and inputting an output signal from the digital-to-analog converter to the analog-to-digital converter in the receiver circuit.

摘要翻译： 在无线发射机和接收机中，由于参考模数转换单元中包含的运算放大器的相位补偿能力，背景校准型模拟 - 数字转换器通常占用大面积。 此外，校准型模拟 - 数字转换器通常需要采样和保持电路来排除布线的寄生电容的影响，从而增加功耗。 通过使用无线发射机和接收机的发射机电路中的数模转换器的输入信号作为校准信号，并将来自数模转换器的输出信号输入到模拟数字校准 数字转换器。

公开(公告)号：US07764216B2

公开(公告)日：2010-07-27

申请号：US12216821

申请日：2008-07-11

申请人： Takashi Oshima ,  Taizo Yamawaki

发明人： Takashi Oshima ,  Taizo Yamawaki

IPC分类号： H03M1/12

CPC分类号： H03M1/1042 ,  H03M1/0673 ,  H03M1/0692 ,  H03M1/183 ,  H03M1/44 ,  H03M1/46

摘要： In an analog-to-digital converter, when a capacitive element with a small capacitance is used in order to reduce power consumption, the characteristics of the analog-to-digital converter deteriorate due to the variation in the specific accuracy. Further, the method of reducing the variation with the specific accuracy causes an increase in the size of the circuit and power consumption. An analog-to-digital converter includes an analog core unit having at least one capacitive element. The capacitive element includes a capacitive bank having plural capacitive element units having substantially the same capacitance value, and the capacitive bank is configured to select one capacitive element unit from the plural capacitive element units with substantially equal probability.

摘要翻译： 在模数转换器中，当使用具有小电容的电容元件以降低功耗时，由于特定精度的变化，模数转换器的特性恶化。 此外，以特定精度减小变化的方法导致电路的尺寸和功耗的增加。 模数转换器包括具有至少一个电容元件的模拟核心单元。 电容元件包括具有多个具有大致相同的电容值的电容元件单元的电容库，并且该电容库被配置为以几乎相等的概率从多个电容元件单元中选择一个电容元件单元。

公开(公告)号：US20090091482A1

公开(公告)日：2009-04-09

申请号：US12244971

申请日：2008-10-03

申请人： Takashi OSHIMA ,  Taizo Yamawaki

发明人： Takashi OSHIMA ,  Taizo Yamawaki

IPC分类号： H03M1/10 ,  H03M1/12

CPC分类号： H03M1/1004 ,  H03M1/002 ,  H03M1/005 ,  H03M1/1009 ,  H03M1/126 ,  H03M1/44

摘要： In a wireless chip receiving the multi-rate data according to the related art, power consumption and a circuit area of an analog-to-digital converter become large. In a digital calibration type analog-to-digital converter including both a reference analog-to-digital conversion unit and a main analog-to-digital conversion unit, when processing the high-sample rate wireless receive signal, both the reference analog-to-digital conversion unit and the main analog-to-digital conversion unit are operated to configure a general digital calibration type analog-to-digital converter, and when processing a low-sample rate wireless receive signal, analog-to-digital conversion is performed by using the reference analog-to-digital conversion unit and operations of the main analog-to-digital conversion unit or the like are stopped to remarkably reduce power consumption.

摘要翻译： 在接收根据现有技术的多速率数据的无线芯片中，功率消耗和模数转换器的电路面积变大。 在包括参考模数转换单元和主模数转换单元的数字校准类型模数转换器中，当处理高抽样率无线接收信号时，参考模拟到数字转换单元 操作数字转换单元和主模拟 - 数字转换单元来配置通用数字校准类型模数转换器，并且当处理低采样率无线接收信号时，执行模拟 - 数字转换 通过使用参考模数转换单元，并且停止主模数转换单元等的操作以显着地降低功耗。