公开(公告)号：US4839860A

公开(公告)日：1989-06-13

申请号：US820523

申请日：1986-01-17

申请人： Takashi Shinoda ,  Kikuo Sakai ,  Masahiro Ogata ,  Hiroshi Kawamoto ,  Yoshiaki Onishi, deceased ,  by Junko Onishi, administratrix

发明人： Takashi Shinoda ,  Kikuo Sakai ,  Masahiro Ogata ,  Hiroshi Kawamoto ,  Yoshiaki Onishi, deceased ,  by Junko Onishi, administratrix

IPC分类号： G06F11/10 ,  G11C17/08

CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G11C17/08

摘要： A semiconductor memory includes a dummy cell for forming a reference potential, a read-only memory cell, and a differential amplifier circuit which receives the reference potential formed by the dummy cell and a signal read out from the memory cell. The differential amplifier circuit is dynamically operated so that the semiconductor memory is made smaller in power consumption and size than conventional units. Moreover, in order to reduce the power consumption, the memory cell is brought into the nonselection state when a predetermined time has passed after being selected. In addition, the semiconductor memory is provided with a compensating circuit in order to make the value of the capacitance connected to a word line for transmitting a selecting signal to the memory cell and the value of the capacitance connected to a dummy word line for transmitting a selecting signal to the dummy cell substantially equal to each other. Thus, the changes in potential of both the selecting signals are made substantially equal to each other. Accordingly, it is possible to reduce malfunctions.

摘要翻译： 半导体存储器包括用于形成参考电位的虚拟单元，只读存储单元和接收由虚设单元形成的参考电位的差分放大器电路和从存储单元读出的信号。 差分放大器电路是动态操作的，使得半导体存储器的功耗和尺寸比常规单元小。 此外，为了降低功耗，当选择了规定时间后，使存储单元变为非选择状态。 此外，半导体存储器设置有补偿电路，以便连接到用于将选择信号发送到存储单元的字线的电容的值和连接到用于发送选择信号的虚拟字线的电容的值 选择到虚拟单元的信号基本相等。 因此，使选择信号的电位变化大致相等。 因此，可以减少故障。

公开(公告)号：US4604749A

公开(公告)日：1986-08-05

申请号：US502636

申请日：1983-06-09

申请人： Takashi Shinoda ,  Kikuo Sakai ,  Masahiro Ogata ,  Hiroshi Kawamoto ,  Yoshiaki Onishi, deceased ,  Junko Onishi, administratrix

发明人： Takashi Shinoda ,  Kikuo Sakai ,  Masahiro Ogata ,  Hiroshi Kawamoto ,  Yoshiaki Onishi, deceased ,  Junko Onishi, administratrix

IPC分类号： G06F11/10 ,  G11C17/08

CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G11C17/08

摘要： YA semiconductor memory is provided with memory cells for storing a plurality of sets of data, each of the sets having check bits. A selecting circuit selects some of the memory cells to form a set in response to a first address signal. The circuit includes an error correcting code circuit, a tristate circuit and a control circuit which forms a control signal to control the tristate circuit. Output terminals of the tristate circuit are coupled with external output terminals of the semiconductor memory. Also, the tristate circuit is controlled by the control signal to bring the external circuit terminals into high impedance at least during the time when the error correcting code circuit is delivering indefinite data.

摘要翻译： YA半导体存储器设置有用于存储多组数据的存储单元，每组具有校验位。 选择电路响应于第一地址信号选择一些存储器单元以形成集合。 电路包括纠错码电路，三态电路和形成控制信号以控制三态电路的控制电路。 三态电路的输出端子与半导体存储器的外部输出端子耦合。 此外，三态电路由控制信号控制，至少在纠错码电路传送不定数据的时间内使外部电路端子变为高阻抗。

公开(公告)号：US4592024A

公开(公告)日：1986-05-27

申请号：US510319

申请日：1983-07-01

申请人： Kikuo Sakai ,  Yoshiaki Onishi, deceased ,  by Junko Onishi, administratrix

发明人： Kikuo Sakai ,  Yoshiaki Onishi, deceased ,  by Junko Onishi, administratrix

IPC分类号： G06F12/16 ,  G06F11/14 ,  G11C29/00 ,  H01L27/10 ,  G11C7/00

CPC分类号： G11C29/70 ,  G06F11/14

摘要： The address of each defective memory cell in a memory cell array is stored within a semiconductor ROM in advance. In parallel with the operation of reading out information from a memory cell of the array, whether or not the address of the memory cell agrees with the previously stored address of a defective memory cell is distinguished. When they agree, a correcting signal is formed. Erroneous data read out from the defective memory cell is inverted on the basis of the correcting signal and thus corrected, whereupon the corrected data is delivered out of the ROM. In using this error data correcting system, a read-out access time delay caused by furnishing the correcting function corresponds to only one stage of a logic circuit which is used for the inversion to correct the erroneous data. Thus, a semiconductor ROM furnished with an error correcting function can be provided without spoiling enhancement in the speed of the read-out operation.

摘要翻译： 存储单元阵列中的每个有缺陷的存储单元的地址预先存储在半导体ROM内。 与从阵列的存储单元读出信息的操作并行地，区分存储器单元的地址是否与先前存储的有缺陷的存储器单元的地址一致。 当它们同意时，形成校正信号。 根据校正信号反转从缺陷存储单元读出的错误数据，由此校正，校正后的数据从ROM中传送出去。 在使用该误差数据校正系统时，通过提供校正功能引起的读出访问时间延迟仅对应于用于反转的逻辑电路的一个阶段来校正错误数据。 因此，可以提供具有纠错功能的半导体ROM，而不会破坏读出操作的速度。

公开(公告)号：US4564925A

公开(公告)日：1986-01-14

申请号：US535056

申请日：1983-09-23

申请人： Yoshiaki Onishi, deceased ,  by Junko Onishi, administratrix ,  Hiroshi Kawamoto ,  Tokumasa Yasui

发明人： Yoshiaki Onishi, deceased ,  by Junko Onishi, administratrix ,  Hiroshi Kawamoto ,  Tokumasa Yasui

IPC分类号： G11C11/403 ,  G11C11/4096 ,  G11C7/00

CPC分类号： G11C11/4096

摘要： A semiconductor memory has dynamic memory cells, such as one-MOS transistor cells, a detector circuit which detects changes in applied address signals, and a timing generator circuit which receives detection outputs of the detector circuit. When the address signals are changed, various timing signals are responsively produced from the timing generator circuit. In response to the timing signals generated in succession, data lines to which the memory cells are coupled are first precharged, and one of the memory cells is selected after the precharge of the data lines. Data delivered from the selected memory cell to the data line is amplified when the operation of a sense amplifier is started. The amplified data is supplied to an external terminal through a column switch, a main amplifier, an output amplifier, etc., which are similarly operated in succession. Since the semiconductor memory of this arrangement forms a pseudo-static memory, it requires only a small number of external timing signals. In order to obtain a desirable pseudo-static memory, a data line precharge level is equalized to half of the supply voltage level, and the sense amplifier is constructed of a CMOS-FET latch circuit. As a result, the period of time from the change of the address signals until the delivery of the output data can be sufficiently shortened. It is therefore possible to form a pseudo-static memory which is, in effect, regarded as a static memory.

摘要翻译： 半导体存储器具有诸如单MOS晶体管单元，检测所施加的地址信号的变化的检测器电路的动态存储单元以及接收检测器电路的检测输出的定时发生器电路。 当地址信号改变时，从定时发生器电路响应地产生各种定时信号。 响应于连续生成的定时信号，首先对存储器单元耦合的数据线进行预充电，并且在数据线的预充电之后选择一个存储单元。 当读出放大器的操作开始时，从选择的存储单元传送到数据线的数据被放大。 放大的数据通过类似地连续操作的列开关，主放大器，输出放大器等提供给外部端子。 由于这种布置的半导体存储器形成伪静态存储器，所以它仅需要少量的外部定时信号。 为了获得期望的伪静态存储器，将数据线预充电电平等于电源电压电平的一半，并且读出放大器由CMOS-FET锁存电路构成。 结果，能够充分地缩短从地址信号变更直到输出数据传送的时间。 因此，可以形成实际上被视为静态存储器的伪静态存储器。