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    SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20090134388A1

    公开(公告)日：2009-05-28

    申请号：US12203409

    申请日：2008-09-03

    申请人： Takashi YAMAUCHI ,  Yoshifumi Nishi ,  Yoshinori Tsuchiya ,  Junji Koga ,  Koichi Kato

    发明人： Takashi YAMAUCHI ,  Yoshifumi Nishi ,  Yoshinori Tsuchiya ,  Junji Koga ,  Koichi Kato

    IPC分类号： H01L29/08 ,  H01L21/06

    CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/7833

    摘要： A semiconductor device having a metal insulator semiconductor field effect transistor (MISFET) with interface resistance-reduced source/drain electrodes is disclosed. This device includes a p-type MISFET formed on a semiconductor substrate. The p-MISFET has a channel region in the substrate, a gate insulating film on the channel region, a gate electrode on the gate insulating film, and a pair of laterally spaced-apart source and drain electrodes on both sides of the channel region. These source/drain electrodes are each formed of a nickel (Ni)-containing silicide layer. The p-MISFET further includes an interface layer which is formed on the substrate side of an interface between the substrate and each source/drain electrode. This interface layer contains magnesium (Mg), calcium (Ca) or barium (Ba) therein. A fabrication method of the semiconductor device is also disclosed.

    摘要翻译： 公开了一种具有金属绝缘体半导体场效应晶体管（MISFET）的半导体器件，具有接口电阻降低的源/漏电极。 该器件包括形成在半导体衬底上的p型MISFET。 p-MISFET在衬底中具有沟道区，沟道区上的栅极绝缘膜，栅极绝缘膜上的栅电极，以及沟道区两侧的一对侧向间隔开的源极和漏极。 这些源极/漏极各自由含镍（Ni）的硅化物层形成。 p-MISFET还包括界面层，该界面层形成在基板和每个源极/漏极之间的界面的基板侧上。 该界面层中含有镁（Mg），钙（Ca）或钡（Ba）。 还公开了半导体器件的制造方法。

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
    2.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 审中-公开
    制造半导体器件和半导体器件的方法

    公开(公告)号：US20090008726A1

    公开(公告)日：2009-01-08

    申请号：US12051947

    申请日：2008-03-20

    申请人： Takashi Yamauchi ,  Yoshifumi Nishi ,  Atsuhiro Kinoshita ,  Yoshinori Tsuchiya ,  Junji Koga ,  Koichi Kato

    发明人： Takashi Yamauchi ,  Yoshifumi Nishi ,  Atsuhiro Kinoshita ,  Yoshinori Tsuchiya ,  Junji Koga ,  Koichi Kato

    IPC分类号： H01L47/00 ,  H01L21/425

    CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/785

    摘要： A method of manufacturing a semiconductor device reducing interface resistance of n-type and p-type MISFETs are provided. According to the method, a gate dielectric film and a gate electrode of the n-type MISFET are formed on a first semiconductor region, a gate dielectric film and a gate electrode of the p-type MISFET are formed on a second semiconductor region, an n-type diffusion layer is formed by ion implantation of As into the first semiconductor region, a first silicide layer is formed by first heat treatment after a first metal containing Ni is deposited on the n-type diffusion layer, the first silicide layer is made thicker by second heat treatment after a second metal containing Ni is deposited on the first silicide layer and second semiconductor region, and third heat treatment is provided after formation of a second silicide layer and ion implantation of B or Mg into the second silicide layer.

    摘要翻译： 提供了制造半导体器件降低n型和p型MISFET的界面电阻的方法。 根据该方法，在第一半导体区域上形成栅极电介质膜和n型MISFET的栅电极，在第二半导体区域上形成p型MISFET的栅极电介质膜和栅电极， 通过将As离子注入第一半导体区域形成n型扩散层，在n型扩散层上沉积含有Ni的第一金属之后，通过第一热处理形成第一硅化物层，制作第一硅化物层 在第一硅化物层和第二半导体区域上沉积含有Ni的第二金属沉积第二热处理之后，在形成第二硅化物层和在第二硅化物层中离子注入B或Mg之后提供第三热处理。

    SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF SAME 失效
    半导体器件及其制造方法

    公开(公告)号：US20080230804A1

    公开(公告)日：2008-09-25

    申请号：US12036703

    申请日：2008-02-25

    申请人： Yoshifumi Nishi ,  Takashi Yamauchi ,  Yoshinori Tsuchiya ,  Junji Koga

    发明人： Yoshifumi Nishi ,  Takashi Yamauchi ,  Yoshinori Tsuchiya ,  Junji Koga

    IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/872 ,  H01L21/283

    CPC分类号： H01L29/47 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/475

    摘要： A semiconductor device having an electrode with reduced electrical contact resistance even where either electrons or holes are majority carriers is disclosed. This device has an n-type diffusion layer and a p-type diffusion layer in a top surface of a semiconductor substrate. The device also has first and second metal wires patterned to overlie the n-type and p-type diffusion layers, respectively, with a dielectric layer interposed therebetween, a first contact electrode for electrical connection between the n-type diffusion layer and the first metal wire, and a second contact electrode for connection between the p-type diffusion layer and the second metal wire. The first contact electrode's portion in contact with the n-type diffusion layer and the second contact electrode's portion contacted with the p-type diffusion layer are each formed of a first conductor that contains a metal and a second conductor containing a rare earth metal.

    摘要翻译： 公开了一种半导体器件，其具有即使电子或空穴为多数载流子的具有降低的电接触电阻的电极。 该器件在半导体衬底的顶表面中具有n型扩散层和p型扩散层。 该装置还具有图案化的第一和第二金属线分别覆盖在n型和p型扩散层之间，介于其间的介电层，用于在n型扩散层和第一金属之间电连接的第一接触电极 电线和用于在p型扩散层和第二金属线之间连接的第二接触电极。 与n型扩散层接触的第一接触电极部分和与p型扩散层接触的第二接触电极部分分别由包含金属的第一导体和含有稀土金属的第二导体形成。

    Semiconductor device and fabrication method of same
    4.
    发明授权
    Semiconductor device and fabrication method of same 失效
    半导体器件及其制造方法

    公开(公告)号：US07642604B2

    公开(公告)日：2010-01-05

    申请号：US12036703

    申请日：2008-02-25

    申请人： Yoshifumi Nishi ,  Takashi Yamauchi ,  Yoshinori Tsuchiya ,  Junji Koga

    发明人： Yoshifumi Nishi ,  Takashi Yamauchi ,  Yoshinori Tsuchiya ,  Junji Koga

    IPC分类号： H01L23/48

    CPC分类号： H01L29/47 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/475

    摘要： A semiconductor device having an electrode with reduced electrical contact resistance even where either electrons or holes are majority carriers is disclosed. This device has an n-type diffusion layer and a p-type diffusion layer in a top surface of a semiconductor substrate. The device also has first and second metal wires patterned to overlie the n-type and p-type diffusion layers, respectively, with a dielectric layer interposed therebetween, a first contact electrode for electrical connection between the n-type diffusion layer and the first metal wire, and a second contact electrode for connection between the p-type diffusion layer and the second metal wire. The first contact electrode's portion in contact with the n-type diffusion layer and the second contact electrode's portion contacted with the p-type diffusion layer are each formed of a first conductor that contains a metal and a second conductor containing a rare earth metal.

    摘要翻译： 公开了一种半导体器件，其具有即使电子或空穴为多数载流子的具有降低的电接触电阻的电极。 该器件在半导体衬底的顶表面中具有n型扩散层和p型扩散层。 该装置还具有图案化的第一和第二金属线分别覆盖在n型和p型扩散层之间，介于其间的介电层，用于在n型扩散层和第一金属之间电连接的第一接触电极 电线和用于在p型扩散层和第二金属线之间连接的第二接触电极。 与n型扩散层接触的第一接触电极部分和与p型扩散层接触的第二接触电极部分分别由包含金属的第一导体和含有稀土金属的第二导体形成。

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE
    5.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE 失效
    制造半导体器件和半导体器件的方法

    公开(公告)号：US20090152652A1

    公开(公告)日：2009-06-18

    申请号：US12323770

    申请日：2008-11-26

    申请人： Yoshifumi NISHI ,  Yoshinori Tsuchiya ,  Takashi Yamauchi ,  Junji Koga

    发明人： Yoshifumi NISHI ,  Yoshinori Tsuchiya ,  Takashi Yamauchi ,  Junji Koga

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/4975 ,  H01L21/26506 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/28537 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L23/485 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed on the surface of the semiconductor substrate by making the first metal and the semiconductor substrate react each other by a first heat treatment. Ions having a mass equal to or larger than atomic weight of Si are implanted into the metal semiconductor compound layer. A second metal is deposited on the metal semiconductor compound layer. An interface layer is formed by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment.

    摘要翻译： 这里描述的是通过降低电极的接触电阻来制造实现更高性能的半导体器件的方法。 在该方法中，在半导体衬底上形成栅极绝缘膜，栅电极。 第一金属是沉积衬底，并且通过使第一金属和半导体衬底通过第一热处理而彼此反应，在半导体衬底的表面上形成金属半导体化合物层。 将具有等于或大于Si原子量的质量的离子注入到金属半导体化合物层中。 第二金属沉积在金属半导体化合物层上。 通过使第二金属通过第二热处理使金属半导体化合物层扩散而使第二金属在金属半导体化合物层和半导体基板之间的界面分离而形成界面层。

    Method of manufacturing MISFET with low contact resistance
    6.
    发明授权
    Method of manufacturing MISFET with low contact resistance 失效
    具有低接触电阻的MISFET的制造方法

    公开(公告)号：US07977182B2

    公开(公告)日：2011-07-12

    申请号：US12323770

    申请日：2008-11-26

    申请人： Yoshifumi Nishi ,  Yoshinori Tsuchiya ,  Takashi Yamauchi ,  Junji Koga

    发明人： Yoshifumi Nishi ,  Yoshinori Tsuchiya ,  Takashi Yamauchi ,  Junji Koga

    IPC分类号： H01L21/8238 ,  H01L29/04 ,  H01L29/10 ,  H01L31/036 ,  H01L21/285

    CPC分类号： H01L29/4975 ,  H01L21/26506 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/28537 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L23/485 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed on the surface of the semiconductor substrate by making the first metal and the semiconductor substrate react each other by a first heat treatment. Ions having a mass equal to or larger than atomic weight of Si are implanted into the metal semiconductor compound layer. A second metal is deposited on the metal semiconductor compound layer. An interface layer is formed by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment.

    摘要翻译： 这里描述的是通过降低电极的接触电阻来制造实现更高性能的半导体器件的方法。 在该方法中，在半导体衬底上形成栅极绝缘膜，栅电极。 第一金属是沉积衬底，并且通过使第一金属和半导体衬底通过第一热处理而彼此反应，在半导体衬底的表面上形成金属半导体化合物层。 将具有等于或大于Si原子量的质量的离子注入到金属半导体化合物层中。 第二金属沉积在金属半导体化合物层上。 通过使第二金属通过第二热处理使金属半导体化合物层扩散而使第二金属在金属半导体化合物层和半导体基板之间的界面分离而形成界面层。