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    DATA PROCESSING APPARATUS AND METHOD, AND PROGRAM
    4.
    发明申请
    DATA PROCESSING APPARATUS AND METHOD, AND PROGRAM 有权
    数据处理设备和方法及程序

    公开(公告)号：US20110246863A1

    公开(公告)日：2011-10-06

    申请号：US13125111

    申请日：2009-10-27

    申请人： Toshiyuki Miyauchi ,  Naoki Yoshimochi

    发明人： Toshiyuki Miyauchi ,  Naoki Yoshimochi

    IPC分类号： H03M13/27 ,  G06F11/08

    CPC分类号： H03M13/2909 ,  G11B20/1833 ,  G11B20/1866 ,  G11B20/1876 ,  G11B2020/1853 ,  G11B2220/2516 ,  G11B2220/2537 ,  H03M13/1102 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/2707 ,  H03M13/2721 ,  H03M13/2778 ,  H03M13/2957

    摘要： The present invention relates to data processing apparatus and method, and a program which make it possible to scatter burst errors with respect to both codes of a product code.A block-wise interleaver performs interleaving A, which is a process of inputting data in the order of the column direction as one direction, and reading the data in the order of the direction diagonally downward to the right, NB bits by NB bits (=block by block) with respect to ND×NB×NA bits of a product code. Next, the block-wise interleaver performs interleaving B, which is a process of inputting data in the order of the column direction as one direction, and reading the data in the order of the row direction as the other direction, NB bits by NB bits with respect to (NC−ND)×NB×NA bits representing the parity portion of an inner code indicated by P, of the product code. The present invention can be applied to, for example, a recording/reproducing apparatus.

    摘要翻译： 数据处理装置和方法技术领域本发明涉及数据处理装置和方法，以及使得可以相对于产品代码的两个代码散布突发错误的程序。 分块交织器执行交织A，其是以列方向的顺序输入数据作为一个方向的过程，并且按照向右对角线向下的方向读取数据，NB位由NB位（= 相对于产品代码的ND×NB×NA比特来逐块地）。 接下来，块式交织器执行交织B，其是以列方向的顺序输入数据作为一个方向的处理，并且以行方向的顺序读取数据作为另一方向，NB位由NB位 相对于代表由P表示的内码的奇偶校验部分的（NC-ND）×NB×NA比特。 本发明可以应用于例如记录/再现装置。

    Data processing apparatus and method, and program
    5.
    发明授权
    Data processing apparatus and method, and program 有权
    数据处理装置及方法及程序

    公开(公告)号：US08539322B2

    公开(公告)日：2013-09-17

    申请号：US13125111

    申请日：2009-10-27

    申请人： Toshiyuki Miyauchi ,  Naoki Yoshimochi

    发明人： Toshiyuki Miyauchi ,  Naoki Yoshimochi

    IPC分类号： H03M13/03

    CPC分类号： H03M13/2909 ,  G11B20/1833 ,  G11B20/1866 ,  G11B20/1876 ,  G11B2020/1853 ,  G11B2220/2516 ,  G11B2220/2537 ,  H03M13/1102 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/2707 ,  H03M13/2721 ,  H03M13/2778 ,  H03M13/2957

    摘要： The present invention relates to data processing apparatus and method, and a program which make it possible to scatter burst errors with respect to both codes of a product code.A block-wise interleaver performs interleaving A, which is a process of inputting data in the order of the column direction as one direction, and reading the data in the order of the direction diagonally downward to the right, NB bits by NB bits (=block by block) with respect to ND×NB×NA bits of a product code. Next, the block-wise interleaver performs interleaving B, which is a process of inputting data in the order of the column direction as one direction, and reading the data in the order of the row direction as the other direction, NB bits by NB bits with respect to (NC−ND)×NB×NA bits representing the parity portion of an inner code indicated by P, of the product code. The present invention can be applied to, for example, a recording/reproducing apparatus.

    摘要翻译： 数据处理装置和方法技术领域本发明涉及数据处理装置和方法，以及使得可以相对于产品代码的两个代码散布突发错误的程序。 分块交织器执行交织A，其是以列方向的顺序输入数据作为一个方向的过程，并且按照向右对角线向下的方向读取数据，NB位由NB位（= 相对于产品代码的ND×NB×NA比特来逐块地）。 接下来，块式交织器执行交织B，其是以列方向的顺序输入数据作为一个方向的处理，并且以行方向的顺序读取数据作为另一方向，NB位由NB位 相对于代表由P表示的内码的奇偶校验部分的（NC-ND）×NB×NA比特。 本发明可以应用于例如记录/再现装置。

    Decoding device and method
    6.
    发明授权
    Decoding device and method 失效
    解码设备和方法

    公开(公告)号：US08166363B2

    公开(公告)日：2012-04-24

    申请号：US12066641

    申请日：2006-09-07

    申请人： Osamu Shinya ,  Takashi Yokokawa ,  Yuji Shinohara ,  Toshiyuki Miyauchi

    发明人： Osamu Shinya ,  Takashi Yokokawa ,  Yuji Shinohara ,  Toshiyuki Miyauchi

    IPC分类号： H03M13/00

    CPC分类号： H04L1/0052 ,  H03M13/1111 ,  H03M13/118 ,  H03M13/6577 ,  H04L1/0057

    摘要： A decoding device and method for decoding an LDPC code with high accuracy while suppressing an increase of the scale of a device. A check node calculator (181) performs check node calculations including calculations of a nonlinear function φ(x) and its inverse function φ−1(x) of the nonlinear function so as to decode an LDPC code. A variable node calculator (103) performs variable node calculation of a variable node so as to decode the LDPC code. The check node calculator (181) has an LUT which receives a fixed-point quantized value expressing a numerical value with a fixed quantization width and outputs the result of the calculation of the nonlinear function φ(x) as a semi-floating point quantized value which is a bit sequence expressing a numerical value with a quantization width determined by a part of a bit sequence and an LUT which receives a semi-floating point quantized value and outputs the result of the calculation of the inverse function φ−1(x) as a fixed point quantized value. The invention can be applied to e.g., a tuner for receiving a satellite broadcast.

    摘要翻译： 一种用于在抑制设备规模增加的同时高精度地解码LDPC码的解码装置和方法。 校验节点计算器（181）执行包括非线性函数的计算的校验节点计算（x）及其非线性函数的反函数＆phgr（-1），以解码LDPC码。 可变节点计算器（103）执行变量节点的可变节点计算，以解码LDPC码。 校验节点计算器（181）具有LUT，其接收表示具有固定量化宽度的数值的定点量化值，并将非线性函数＆amp;（x）的计算结果作为半浮点数量化 值，其是表示具有由位序列的一部分确定的量化宽度的数值的位序列和接收半浮点量化值的LUT，并输出反函数的计算结果＆phgr; -1（ x）作为固定点量化值。 本发明可以应用于例如用于接收卫星广播的调谐器。

    Decoding method and decoding apparatus as well as program
    7.
    发明授权
    Decoding method and decoding apparatus as well as program 有权
    解码方式和解码装置以及程序

    公开(公告)号：US08103945B2

    公开(公告)日：2012-01-24

    申请号：US11959551

    申请日：2007-12-19

    申请人： Makiko Yamamoto ,  Satoshi Okada ,  Toshiyuki Miyauchi ,  Takashi Yokokawa

    发明人： Makiko Yamamoto ,  Satoshi Okada ,  Toshiyuki Miyauchi ,  Takashi Yokokawa

    IPC分类号： G06F11/00

    CPC分类号： H03M13/114 ,  H03M13/1111 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2936 ,  H03M13/2948 ,  H03M13/3905 ,  H03M13/4146

    摘要： A decoding method for sorting received words in the order of the magnitude of the reliability of the received words, performing belief propagation using a parity check matrix diagonalized in the order to update the reliabilities, and repetitively performing the sorting and the belief propagation for the updated values, includes an inner repeated decoding process step of performing belief propagation using a parity check matrix diagonalized in an order of columns corresponding to symbols having comparatively low reliability values of the received words to update the reliability and repetitively performing the belief propagation based on the updated reliability; the inner repeated decoding process step in the second or later cycle of repetition thereof including diagonalization of the parity check matrix for restricted ones of the columns of the parity check matrix.

    摘要翻译： 一种用于按接收字的可靠性大小的顺序对接收到的字进行分类的解码方法，使用以对等化的奇偶校验矩阵来执行置信传播，以更新可靠性，并且重复地执行用于更新的可更新的排序和置信传播 值包括内部重复解码处理步骤，其使用对应于与所接收到的字的具有相对低的可靠性值的符号相对应的列的顺序对角化的奇偶校验矩阵来执行置信传播，以更新可靠性并基于更新后的重新执行置信传播 可靠性; 内部重复解码处理步骤在其重复的第二或更晚的循环中，包括奇偶校验矩阵的有限列的奇偶校验矩阵的对角化。

    Decoding Device and Method
    8.
    发明申请
    Decoding Device and Method 失效
    解码设备和方法

    公开(公告)号：US20090304111A1

    公开(公告)日：2009-12-10

    申请号：US12066641

    申请日：2006-09-07

    申请人： Osamu Shinya ,  Takashi Yokokawa ,  Yuji Shinohara ,  Toshiyuki Miyauchi

    发明人： Osamu Shinya ,  Takashi Yokokawa ,  Yuji Shinohara ,  Toshiyuki Miyauchi

    IPC分类号： H03K9/00

    CPC分类号： H04L1/0052 ,  H03M13/1111 ,  H03M13/118 ,  H03M13/6577 ,  H04L1/0057

    摘要： A decoding device and method for decoding an LDPC code with high accuracy while suppressing an increase of the scale of a device. A check node calculator (181) performs check node calculations including calculations of a nonlinear function φ(x) and its inverse function φ−1(x) of the nonlinear function so as to decode an LDPC code. A variable node calculator (103) performs variable node calculation of a variable node so as to decode the LDPC code. The check node calculator (181) has an LUT which receives a fixed-point quantized value expressing a numerical value with a fixed quantization width and outputs the result of the calculation of the nonlinear function φ(x) as a semi-floating point quantized value which is a bit sequence expressing a numerical value with a quantization width determined by a part of a bit sequence and an LUT which receives a semi-floating point quantized value and outputs the result of the calculation of the inverse function φ−1(x) as a fixed point quantized value. The invention can be applied to e.g., a tuner for receiving a satellite broadcast.

    摘要翻译： 一种用于在抑制设备规模增加的同时高精度地解码LDPC码的解码装置和方法。 校验节点计算器（181）执行包括非线性函数phi（x）及其反函数phi-1（x）的计算的校验节点计算，以解码LDPC码。 可变节点计算器（103）执行变量节点的可变节点计算，以解码LDPC码。 校验节点计算器（181）具有LUT，其接收具有固定量化宽度的表示数值的定点量化值，并将非线性函数phi（x）的计算结果输出为半浮点量化值 其是表示具有由位序列的一部分确定的量化宽度的数值的位序列和接收半浮点量化值的LUT，并输出反函数phi-1（x）的计算结果， 作为固定点量化值。 本发明可以应用于例如用于接收卫星广播的调谐器。

    Decoder an decoding method
    9.
    发明授权
    Decoder an decoding method 失效
    解码器解码方法

    公开(公告)号：US07051270B2

    公开(公告)日：2006-05-23

    申请号：US10110670

    申请日：2001-08-20

    申请人： Toshiyuki Miyauchi ,  Masayuki Hattori ,  Kouhei Yamamoto ,  Takashi Yokokawa

    发明人： Toshiyuki Miyauchi ,  Masayuki Hattori ,  Kouhei Yamamoto ,  Takashi Yokokawa

    IPC分类号： H03M13/03 ,  H03M13/00

    CPC分类号： H03M13/3905 ,  H03M13/258 ,  H03M13/27 ,  H03M13/29 ,  H03M13/2957 ,  H03M13/2972 ,  H03M13/6337 ,  H03M13/6577 ,  H03M13/658

    摘要： A decoder that receives, as input, probability information AMP/CR×yt. This probability information is obtained by dividing a channel value obtained by multiplication of received value yt and a predetermined coefficient AMP by the first additive coefficient CR for regulating the amplitude of the received value yt and the probability information 1/CA×APPt obtained by multiplying the a priori probability information APPt by the reciprocal of the second additive coefficient CA for regulating the amplitude of the a priori probability information APPt to a soft-output decoding circuit. The soft-output decoding circuit, which may be a large scale intergrated circuit, generates log soft-output CI×Iλt and/or external information 1/CA×EXt using additive coefficients for regulating the amplitude of arithmetic operations in the inside of the soft-output decoding circuit.

    摘要翻译： 接收作为输入的概率信息的解码器。 该概率信息是通过将通过接收值y T 与预定系数AMP乘以获得的信道值除以第一加法系数C SUB来获得的，以用于调节 通过将先验概率信息APP＆lt; T＆gt;＆lt;＆gt;＆lt; T＆gt;获得的概率信息1 / C A xAPP＆lt; SUB>通过第二加法系数C A A A的倒数，用于将先验概率信息APP 的振幅调整到软输出解码电路。 可以是大规模集成电路的软输出解码电路生成日志软输出C 1和/或外部信息1 / C＆lt; 使用用于调节软输出解码电路内部的算术运算幅度的加法系数的XEXT。

    RECEIVING APPARATUS, RECEIVING METHOD, AND PROGRAM
    10.
    发明申请
    RECEIVING APPARATUS, RECEIVING METHOD, AND PROGRAM 有权
    接收设备，接收方法和程序

    公开(公告)号：US20100080330A1

    公开(公告)日：2010-04-01

    申请号：US12567856

    申请日：2009-09-28

    申请人： Hidetoshi KAWAUCHI ,  Masayuki Hattori ,  Toshiyuki Miyauchi ,  Takashi Yokokawa ,  Kazuhiro Shimizu ,  Kazuhisa Funamoto

    发明人： Hidetoshi KAWAUCHI ,  Masayuki Hattori ,  Toshiyuki Miyauchi ,  Takashi Yokokawa ,  Kazuhiro Shimizu ,  Kazuhisa Funamoto

    IPC分类号： H04B1/10

    CPC分类号： H04L27/2662 ,  H04L25/0232 ,  H04L25/03159 ,  H04L27/2656 ,  H04L27/2665

    摘要： Disclosed herein is a receiving apparatus including: first to third position determination sections configured to determine the start position of an FFT interval which serves as a signal interval targeted for FFT by an FFT section; a selection section configured to select one of those start positions of the FFT interval which are determined by the first through the third position determination section; and the FFT section configured to perform FFT on the OFDM time domain signal by regarding the start position selected by the selection section as the start position of the FFT interval in order to generate the first OFDM frequency domain signal.

    摘要翻译： 本发明公开了一种接收装置，包括：第一至第三位置确定部分，被配置为确定FFT间隔的起始位置，其作为由FFT部分进行FFT的信号间隔; 选择部，被配置为选择由所述第一至第三位置确定部确定的所述FFT间隔的那些起始位置之一; FFT部，被配置为通过将由选择部选择出的开始位置作为FFT间隔的开始位置，对OFDM时域信号进行FFT，以生成第一OFDM频域信号。