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    SEMICONDUCTOR DEVICE HAVING LEVEL SHIFT CIRCUIT
    1.
    发明申请
    SEMICONDUCTOR DEVICE HAVING LEVEL SHIFT CIRCUIT 有权
    具有电平转换电路的半导体器件

    公开(公告)号：US20120134439A1

    公开(公告)日：2012-05-31

    申请号：US13286665

    申请日：2011-11-01

    申请人： Takenori Sato ,  Yoji Idei ,  Hiromasa Noda

    发明人： Takenori Sato ,  Yoji Idei ,  Hiromasa Noda

    IPC分类号： H04L27/00 ,  H03K19/0175 ,  H03L5/00

    CPC分类号： G11C11/4093 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008 ,  H03K3/356104

    摘要： A semiconductor device includes: two level shift circuits having substantially the same circuit configuration; an input circuit that supplies complementary input signals to the level shift circuits, respectively; and an output circuit that converts complementary output signals output from the level shift circuits into in-phase signals and then short-circuits the in-phase signals. According to the present invention, the two level shift circuits having substantially the same circuit configuration are used, and the complementary output signals output from the level shift circuits are converted into in-phase signals before short-circuited. This avoids almost any occurrence of a through current due to a difference in operating speed between the level shift circuits.

    摘要翻译： 半导体器件包括：具有基本相同的电路配置的两个电平移位电路; 输入电路，分别向电平移位电路提供互补输入信号; 以及输出电路，其将从电平移位电路输出的互补输出信号转换为同相信号，然后使同相信号短路。 根据本发明，使用具有基本相同电路结构的两电平移位电路，并且从电平移位电路输出的互补输出信号在短路之前被转换为同相信号。 由于电平移位电路之间的操作速度的差异，几乎不会发生任何直流电流的发生。

    Semiconductor device having level shift circuit
    2.
    发明授权
    Semiconductor device having level shift circuit 有权
    具有电平移位电路的半导体器件

    公开(公告)号：US08891318B2

    公开(公告)日：2014-11-18

    申请号：US13286665

    申请日：2011-11-01

    申请人： Takenori Sato ,  Yoji Idei ,  Hiromasa Noda

    发明人： Takenori Sato ,  Yoji Idei ,  Hiromasa Noda

    IPC分类号： G11C7/10 ,  G11C7/22 ,  H03K19/0175 ,  G11C11/4076 ,  G11C29/02 ,  H03K3/356 ,  G11C29/50 ,  G11C11/4093

    CPC分类号： G11C11/4093 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008 ,  H03K3/356104

    摘要： A semiconductor device includes: two level shift circuits having substantially the same circuit configuration; an input circuit that supplies complementary input signals to the level shift circuits, respectively; and an output circuit that converts complementary output signals output from the level shift circuits into in-phase signals and then short-circuits the in-phase signals. According to the present invention, the two level shift circuits having substantially the same circuit configuration are used, and the complementary output signals output from the level shift circuits are converted into in-phase signals before short-circuited. This avoids almost any occurrence of a through current due to a difference in operating speed between the level shift circuits.

    摘要翻译： 半导体器件包括：具有基本相同的电路配置的两个电平移位电路; 输入电路，分别向电平移位电路提供互补输入信号; 以及输出电路，其将从电平移位电路输出的互补输出信号转换为同相信号，然后使同相信号短路。 根据本发明，使用具有基本相同电路结构的两电平移位电路，并且从电平移位电路输出的互补输出信号在短路之前被转换为同相信号。 由于电平移位电路之间的操作速度的差异，几乎不会发生任何直流电流的发生。

    SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 失效
    半导体存储器件

    公开(公告)号：US20090016126A1

    公开(公告)日：2009-01-15

    申请号：US12170561

    申请日：2008-07-10

    申请人： Kazuhiro Teramoto ,  Yoji Idei ,  Takenori Sato

    发明人： Kazuhiro Teramoto ,  Yoji Idei ,  Takenori Sato

    IPC分类号： G11C7/00 ,  G11C8/08

    CPC分类号： G11C29/02 ,  G11C29/025 ,  G11C29/50008 ,  G11C2029/1204 ,  G11C2029/5006

    摘要： A semiconductor memory device is provided that is capable of detecting a short circuit defect to be detected in a memory array without causing an error due to off-current of a sense amplifier circuit. Sense amplifier circuits amplify a potential between a pair of bit lines, which occurs based on potential of memory cells selected by driving word lines and bit lines. Selection transistors are provided between the bit lines and the sense amplifier circuits. A word-SE interval control circuit included in an X timing generating circuit turns off the selection transistors and disconnects the bit lines from the sense amplifier circuits based on a signal representing a test state for expanded time when a test to expand an interval between word line driving and activation of the sense amplifier circuits and detect defect sites of the bit lines is performed.

    摘要翻译： 提供一种半导体存储器件，其能够检测在存储器阵列中要检测的短路缺陷，而不会由于读出放大器电路的截止电流而引起误差。 感测放大器电路根据通过驱动字线和位线选择的存储器单元的电位放大一对位线之间的电位。 选择晶体管设置在位线和读出放大器电路之间。 包括在X定时发生电路中的字SE间隔控制电路关闭选择晶体管，并且当扩展字线之间的间隔的测试时，基于表示用于扩展时间的测试状态的信号，从读出放大器电路断开位线 执行感测放大器电路的驱动和激活并检测位线的缺陷位置。

    Semiconductor storage device
    4.
    发明授权
    Semiconductor storage device 有权
    半导体存储设备

    公开(公告)号：US07719911B2

    公开(公告)日：2010-05-18

    申请号：US12169873

    申请日：2008-07-09

    申请人： Kazuhiro Teramoto ,  Yoji Idei ,  Takenori Sato ,  Hiroki Fujisawa

    发明人： Kazuhiro Teramoto ,  Yoji Idei ,  Takenori Sato ,  Hiroki Fujisawa

    IPC分类号： G11C7/00

    CPC分类号： G11C5/14 ,  G11C7/08 ,  G11C11/4091

    摘要： A semiconductor storage device is provided which enables use of an overdrive method at low voltage and for a small device area. The semiconductor device includes: memory cells; sense amplifiers, each having P-channel and N-channel MOS transistors and amplifying a signal read from a memory cell; a first power supply line connected to a source terminal of the P-channel MOS transistor provided in each of the sense amplifiers; a second power supply line which supplies an overdrive voltage to the sense amplifiers at a potential higher than a write potential of the memory cell; a third power supply line connected to an external power supply, a connection element which connects and disconnects the first power supply line and the second power supply line; a capacitance element connected to the second power supply line; and a resistance element inserted between the second power supply line and the third power supply line.

    摘要翻译： 提供一种半导体存储装置，其能够在低电压和小的装置区域中使用过驱动方法。 半导体器件包括：存储单元; 读出放大器，每个具有P沟道和N沟道MOS晶体管，并放大从存储单元读取的信号; 连接到设置在每个读出放大器中的P沟道MOS晶体管的源极端子的第一电源线; 第二电源线，其以比存储单元的写入电位高的电位向读出放大器提供过驱动电压; 连接到外部电源的第三电源线，连接和断开第一电源线和第二电源线的连接元件; 连接到第二电源线的电容元件; 以及插入在第二电源线和第三电源线之间的电阻元件。

    SEMICONDUCTOR STORAGE DEVICE
    5.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 有权
    半导体存储设备

    公开(公告)号：US20090016139A1

    公开(公告)日：2009-01-15

    申请号：US12169873

    申请日：2008-07-09

    申请人： Kazuhiro Teramoto ,  Yoji Idei ,  Takenori Sato ,  Hiroki Fujisawa

    发明人： Kazuhiro Teramoto ,  Yoji Idei ,  Takenori Sato ,  Hiroki Fujisawa

    IPC分类号： G11C5/14

    CPC分类号： G11C5/14 ,  G11C7/08 ,  G11C11/4091

    摘要： A semiconductor storage device is provided which enables use of an overdrive method at low voltage and for a small device area. The semiconductor device includes: memory cells; sense amplifiers, each having P-channel and N-channel MOS transistors and amplifying a signal read from a memory cell; a first power supply line connected to a source terminal of the P-channel MOS transistor provided in each of the sense amplifiers; a second power supply line which supplies an overdrive voltage to the sense amplifiers at a potential higher than a write potential of the memory cell; a third power supply line connected to an external power supply, a connection element which connects and disconnects the first power supply line and the second power supply line; a capacitance element connected to the second power supply line; and a resistance element inserted between the second power supply line and the third power supply line.

    摘要翻译： 提供一种半导体存储装置，其能够在低电压和小的装置区域中使用过驱动方法。 半导体器件包括：存储单元; 读出放大器，每个具有P沟道和N沟道MOS晶体管，并放大从存储单元读取的信号; 连接到设置在每个读出放大器中的P沟道MOS晶体管的源极端子的第一电源线; 第二电源线，其以比存储单元的写入电位高的电位向读出放大器提供过驱动电压; 连接到外部电源的第三电源线，连接和断开第一电源线和第二电源线的连接元件; 连接到第二电源线的电容元件; 以及插入在第二电源线和第三电源线之间的电阻元件。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07649790B2

    公开(公告)日：2010-01-19

    申请号：US12170561

    申请日：2008-07-10

    申请人： Kazuhiro Teramoto ,  Yoji Idei ,  Takenori Sato

    发明人： Kazuhiro Teramoto ,  Yoji Idei ,  Takenori Sato

    IPC分类号： G11C29/00

    CPC分类号： G11C29/02 ,  G11C29/025 ,  G11C29/50008 ,  G11C2029/1204 ,  G11C2029/5006

    摘要： A semiconductor memory device is provided that is capable of detecting a short circuit defect to be detected in a memory array without causing an error due to off-current of a sense amplifier circuit. Sense amplifier circuits amplify a potential between a pair of bit lines, which occurs based on potential of memory cells selected by driving word lines and bit lines. Selection transistors are provided between the bit lines and the sense amplifier circuits. A word-SE interval control circuit included in an X timing generating circuit turns off the selection transistors and disconnects the bit lines from the sense amplifier circuits based on a signal representing a test state for expanded time when a test to expand an interval between word line driving and activation of the sense amplifier circuits and detect defect sites of the bit lines is performed.

    摘要翻译： 提供一种半导体存储器件，其能够检测在存储器阵列中要检测的短路缺陷，而不会由于读出放大器电路的截止电流而引起误差。 感测放大器电路根据通过驱动字线和位线选择的存储器单元的电位放大一对位线之间的电位。 选择晶体管设置在位线和读出放大器电路之间。 包括在X定时发生电路中的字SE间隔控制电路关闭选择晶体管，并且当扩展字线之间的间隔的测试时，基于表示用于扩展时间的测试状态的信号，从读出放大器电路断开位线 执行感测放大器电路的驱动和激活并检测位线的缺陷位置。

    Semiconductor memory device, memory controller that controls the same, and information processing system
    9.
    发明授权
    Semiconductor memory device, memory controller that controls the same, and information processing system 失效
    半导体存储器件，控制器的存储器控​​制器以及信息处理系统

    公开(公告)号：US08363503B2

    公开(公告)日：2013-01-29

    申请号：US12776964

    申请日：2010-05-10

    申请人： Takenori Sato ,  Hiroki Fujisawa

    发明人： Takenori Sato ,  Hiroki Fujisawa

    IPC分类号： G11C7/00

    CPC分类号： G11C5/14 ,  G11C5/144 ,  G11C7/1066 ,  G11C7/20 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4072 ,  G11C11/4076

    摘要： To include a power-down control circuit that suspends an operation of a predetermined internal circuit in response to a power-down command, and an external terminal to which a selection signal is input from outside simultaneously with issuance of a power-down command. The power-down control circuit suspends an operation of a DLL circuit when the selection signal is at a low level, and continues an operation of the DLL circuit when the selection signal is at a high level. According to the present invention, by using the selection signal input simultaneously with a power-down command, mode selection can be made on-the-fly.

    摘要翻译： 包括一个断电控制电路，其响应于断电指令暂停预定的内部电路的操作，以及外部端子，同时从外部输入选择信号，同时发出断电命令。 当选择信号处于低电平时，断电控制电路暂停DLL电路的操作，并且当选择信号处于高电平时继续DLL电路的操作。 根据本发明，通过使用与停电命令同时输入的选择信号，可以进行模式选择。

    Semiconductor device operates on external and internal power supply voltages and data processing system including the same
    10.
    发明授权
    Semiconductor device operates on external and internal power supply voltages and data processing system including the same 有权
    半导体器件对外部和内部电源电压和包括其的数据处理系统进行操作

    公开(公告)号：US08923077B2

    公开(公告)日：2014-12-30

    申请号：US13614845

    申请日：2012-09-13

    申请人： Takenori Sato

    发明人： Takenori Sato

    IPC分类号： G11C7/00 ,  G11C7/10

    CPC分类号： G11C7/1057

    摘要： The semiconductor device including an output terminal; and an output unit coupled to the output terminal. The output unit includes an output buffer coupled to the output terminal and operating on a first power supply voltage, a first control circuit operating on a second power supply voltage, receiving an impedance adjustment signal and a data signal and making the output buffer drive the output terminal to a first logic level designated by the data signal with impedance designated by the impedance adjustment signal, and a level shifter coupled between the output buffer and the first control circuit. The second power supply voltage is smaller in level than the first power supply voltage. The level shifter includes a first circuit portion operating on the second power supply voltage and a second circuit portion operating on the first power supply voltage.

    摘要翻译： 该半导体器件包括输出端子; 以及耦合到输出端子的输出单元。 输出单元包括耦合到输出端并输出第一电源电压的输出缓冲器，在第二电源电压上工作的第一控制电路，接收阻抗调整信号和数据信号，并使输出缓冲器驱动输出 端子连接到由阻抗调节信号指定的阻抗的数据信号指定的第一逻辑电平，以及耦合在输出缓冲器和第一控制电路之间的电平移位器。 第二电源电压的电平小于第一电源电压。 电平移位器包括在第二电源电压上操作的第一电路部分和在第一电源电压上操作的第二电路部分。