公开(公告)号：US20080203402A1

公开(公告)日：2008-08-28

申请号：US12071717

申请日：2008-02-26

申请人： Takeshi Endo ,  Tsuyoshi Yamamoto ,  Eiichi Okuno

发明人： Takeshi Endo ,  Tsuyoshi Yamamoto ,  Eiichi Okuno

IPC分类号： H01L29/15 ,  H01L21/3205 ,  H01L21/336

CPC分类号： H01L29/7828 ,  H01L21/049 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/51 ,  H01L29/66068

摘要： A SiC semiconductor device includes: a SiC substrate having a main surface; a channel region on the substrate; first and second impurity regions on upstream and downstream sides of the channel region, respectively; a gate on the channel region through a gate insulating film. The channel region for flowing current between the first and second impurity regions is controlled by a voltage applied to the gate. An interface between the channel region and the gate insulating film has a hydrogen concentration equal to or greater than 2.6×1020 cm−3. The interface provides a channel surface perpendicular to a (0001)-orientation plane.

摘要翻译： SiC半导体器件包括：具有主表面的SiC衬底; 衬底上的沟道区; 分别在通道区域的上游侧和下游侧的第一和第二杂质区域; 通过栅极绝缘膜在沟道区上形成栅极。 用于在第一和第二杂质区域之间流动电流的沟道区域由施加到栅极的电压来控制。 沟道区域和栅极绝缘膜之间的界面的氢浓度等于或大于2.6×10 20 cm -3。 界面提供垂直于（0001）取向平面的通道表面。

公开(公告)号：US07824995B2

公开(公告)日：2010-11-02

申请号：US12071717

申请日：2008-02-26

申请人： Takeshi Endo ,  Tsuyoshi Yamamoto ,  Eiichi Okuno

发明人： Takeshi Endo ,  Tsuyoshi Yamamoto ,  Eiichi Okuno

IPC分类号： H01L29/72

CPC分类号： H01L29/7828 ,  H01L21/049 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/51 ,  H01L29/66068

摘要： A SiC semiconductor device includes: a SiC substrate having a main surface; a channel region on the substrate; first and second impurity regions on upstream and downstream sides of the channel region, respectively; a gate on the channel region through a gate insulating film. The channel region for flowing current between the first and second impurity regions is controlled by a voltage applied to the gate. An interface between the channel region and the gate insulating film has a hydrogen concentration equal to or greater than 2.6×1020 cm−3. The interface provides a channel surface perpendicular to a (0001)-orientation plane.

摘要翻译： SiC半导体器件包括：具有主表面的SiC衬底; 衬底上的沟道区; 分别在通道区域的上游侧和下游侧的第一和第二杂质区域; 通过栅极绝缘膜在沟道区上形成栅极。 用于在第一和第二杂质区域之间流动电流的沟道区域由施加到栅极的电压来控制。 沟道区域和栅极绝缘膜之间的界面的氢浓度等于或大于2.6×1020cm-3。 界面提供垂直于（0001）取向平面的通道表面。

公开(公告)号：US20070045631A1

公开(公告)日：2007-03-01

申请号：US11511236

申请日：2006-08-29

申请人： Takeshi Endo ,  Tsuyoshi Yamamoto ,  Jun Kawai ,  Kensaku Yamamoto ,  Eiichi Okuno

发明人： Takeshi Endo ,  Tsuyoshi Yamamoto ,  Jun Kawai ,  Kensaku Yamamoto ,  Eiichi Okuno

IPC分类号： H01L31/0312

CPC分类号： H01L21/049 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7828 ,  H01L29/7838

摘要： A silicon carbide semiconductor device having a MOS structure includes: a substrate; a channel area in the substrate; a first impurity area; a second impurity area; a gate insulating film on the channel area; and a gate on the gate insulating film. The channel area provides an electric current path. The channel area and the gate insulating film have an interface therebetween. The interface includes a dangling bond, which is terminated by a hydrogen atom or a hydroxyl. The interface has a hydrogen concentration equal to or larger than 2.6×1020 cm−3.

摘要翻译： 具有MOS结构的碳化硅半导体器件包括：衬底; 衬底中的通道区域; 第一杂质区; 第二杂质区域; 通道区域上的栅极绝缘膜; 和栅极绝缘膜上的栅极。 通道区域提供电流通路。 沟道区域和栅极绝缘膜之间具有界面。 界面包括由氢原子或羟基封端的悬挂键。 界面的氢浓度等于或大于2.6×10 20 cm -3。

公开(公告)号：US07993966B2

公开(公告)日：2011-08-09

申请号：US11511236

申请日：2006-08-29

申请人： Takeshi Endo ,  Tsuyoshi Yamamoto ,  Jun Kawai ,  Kensaku Yamamoto ,  Eiichi Okuno

发明人： Takeshi Endo ,  Tsuyoshi Yamamoto ,  Jun Kawai ,  Kensaku Yamamoto ,  Eiichi Okuno

IPC分类号： H01L21/336

CPC分类号： H01L21/049 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7828 ,  H01L29/7838

摘要： A silicon carbide semiconductor device having a MOS structure includes: a substrate; a channel area in the substrate; a first impurity area; a second impurity area; a gate insulating film on the channel area; and a gate on the gate insulating film. The channel area provides an electric current path. The channel area and the gate insulating film have an interface therebetween. The interface includes a dangling bond, which is terminated by a hydrogen atom or a hydroxyl. The interface has a hydrogen concentration equal to or larger than 2.6×1020 cm−3.

摘要翻译： 具有MOS结构的碳化硅半导体器件包括：衬底; 衬底中的通道区域; 第一杂质区; 第二杂质区域; 通道区域上的栅极绝缘膜; 和栅极绝缘膜上的栅极。 通道区域提供电流通路。 沟道区域和栅极绝缘膜之间具有界面。 界面包括由氢原子或羟基封端的悬挂键。 该界面的氢浓度等于或大于2.6×1020cm-3。

公开(公告)号：US20080283845A1

公开(公告)日：2008-11-20

申请号：US12219007

申请日：2008-07-15

申请人： Takeshi Endo ,  Tsuyoshi Yamamoto ,  Jun Kawai ,  Kensaku Yamamoto ,  Eiichi Okuno

发明人： Takeshi Endo ,  Tsuyoshi Yamamoto ,  Jun Kawai ,  Kensaku Yamamoto ,  Eiichi Okuno

IPC分类号： H01L29/15

CPC分类号： H01L21/049 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7828 ,  H01L29/7838

摘要： A silicon carbide semiconductor device having a MOS structure includes: a substrate; a channel area in the substrate; a first impurity area; a second impurity area; a gate insulating film on the channel area; and a gate on the gate insulating film. The channel area provides an electric current path. The channel area and the gate insulating film have an interface therebetween. The interface includes a dangling bond, which is terminated by a hydrogen atom or a hydroxyl. The interface has a hydrogen concentration equal to or larger than 2.6×1020 cm−3.

摘要翻译： 具有MOS结构的碳化硅半导体器件包括：衬底; 衬底中的通道区域; 第一杂质区; 第二杂质区域; 通道区域上的栅极绝缘膜; 和栅极绝缘膜上的栅极。 通道区域提供电流通路。 沟道区域和栅极绝缘膜之间具有界面。 界面包括由氢原子或羟基封端的悬挂键。 界面的氢浓度等于或大于2.6×10 20 cm -3。

公开(公告)号：US20090114969A1

公开(公告)日：2009-05-07

申请号：US12289624

申请日：2008-10-30

申请人： Naohiro Suzuki ,  Yuuichi Takeuchi ,  Takeshi Endo ,  Eiichi Okuno ,  Toshimasa Yamamoto

发明人： Naohiro Suzuki ,  Yuuichi Takeuchi ,  Takeshi Endo ,  Eiichi Okuno ,  Toshimasa Yamamoto

IPC分类号： H01L29/94 ,  H01L21/04 ,  H01L29/68

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/7391 ,  H01L29/7397 ,  H01L29/7828

摘要： An SiC semiconductor device and a related manufacturing method are disclosed having a structure provided with a p+-type deep layer formed in a depth equal to or greater than that of a trench to cause a depletion layer between at a PN junction between the p+-type deep layer and an n−-type drift layer to extend into the n−-type drift layer in a remarkable length, making it difficult for a high voltage, resulting from an adverse affect arising from a drain voltage, to enter a gate oxide film. This results in a capability of minimizing an electric field concentration in the gate oxide film, i.e., an electric field concentration occurring at the gate oxide film at a bottom wall of the trench.

摘要翻译： 公开了一种SiC半导体器件和相关制造方法，其具有设置有等于或大于沟槽深度形成的p +型深层的结构，以在p +型之间的PN结处引起耗尽层 深层和n型漂移层以非常长的长度延伸到n型漂移层中，使得由于漏极电压引起的不利影响导致的高电压难以进入栅极氧化膜 。 这导致使栅极氧化膜中的电场浓度最小化的能力，即在沟槽的底壁处的栅极氧化膜处发生的电场浓度。

公开(公告)号：US07825017B2

公开(公告)日：2010-11-02

申请号：US12406578

申请日：2009-03-18

申请人： Takeo Yamamoto ,  Takeshi Endo ,  Eiichi Okuno ,  Masaki Konishi

发明人： Takeo Yamamoto ,  Takeshi Endo ,  Eiichi Okuno ,  Masaki Konishi

IPC分类号： H01L21/28 ,  H01L21/283 ,  H01L21/44 ,  H01L21/441 ,  H01L31/0312 ,  H01L29/47

CPC分类号： H01L29/872 ,  H01L21/0495 ,  H01L29/0611 ,  H01L29/063 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/7395 ,  H01L29/8083 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2924/0002 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

摘要： A silicon carbide semiconductor device provided as a semiconductor chip includes a substrate, a drift layer on the substrate, an insulation film on the drift layer, a semiconductor element formed in a cell region of the drift layer, a surface electrode formed on the drift layer and electrically coupled to the semiconductor element through an opening of the insulation film, and a passivation film formed above the drift layer around the periphery of the cell region to cover an outer edge of the surface electrode. The passivation film has an opening through which the surface electrode is exposed outside. A surface of the passivation film is made uneven to increase a length from an inner edge of the opening of the passivation film to a chip edge measured along the surface of the passivation film.

摘要翻译： 设置为半导体芯片的碳化硅半导体器件包括衬底，衬底上的漂移层，漂移层上的绝缘膜，形成在漂移层的单元区域中的半导体元件，形成在漂移层上的表面电极 并且通过所述绝缘膜的开口电耦合到所述半导体元件，以及钝化膜，所述钝化膜形成在所述电池区周围的漂移层上方以覆盖所述表面电极的外边缘。 钝化膜具有开口，表面电极通过该开口暴露在外部。 钝化膜的表面被制成不均匀以增加从钝化膜的开口的内边缘到沿着钝化膜的表面测量的芯片边缘的长度。

公开(公告)号：US07365363B2

公开(公告)日：2008-04-29

申请号：US11108906

申请日：2005-04-19

申请人： Jun Kojima ,  Takeshi Endo ,  Eiichi Okuno ,  Yoshihito Mitsuoka ,  Yoshiyuki Hisada ,  Hideo Matsuki

发明人： Jun Kojima ,  Takeshi Endo ,  Eiichi Okuno ,  Yoshihito Mitsuoka ,  Yoshiyuki Hisada ,  Hideo Matsuki

IPC分类号： H01L31/0312

CPC分类号： H01L29/66068 ,  H01L21/02024 ,  H01L29/045 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7828

摘要： A silicon carbide semiconductor device includes: a semiconductor substrate having a principal surface and a backside surface; a drift layer disposed on the principal surface; a base region disposed on the drift layer; a source region disposed on the base region; a surface channel layer disposed on both of the drift layer and the base region for connecting between the source region and the drift layer; a gate insulation film disposed on the surface channel layer and including a high dielectric constant film; a gate electrode disposed on the gate insulation film; a source electrode disposed on the source region; and a backside electrode disposed on the backside surface.

摘要翻译： 碳化硅半导体器件包括：具有主表面和背面的半导体衬底; 设置在主表面上的漂移层; 设置在漂移层上的基极区域; 设置在所述基底区域上的源极区域; 设置在所述漂移层和所述基极区域两者上的表面沟道层，用于在所述源极区域和所述漂移层之间连接; 栅极绝缘膜，设置在所述表面沟道层上并且包括高介电常数膜; 设置在所述栅极绝缘膜上的栅电极; 源电极，其设置在所述源极区域上; 以及设置在所述背面上的背面电极。

公开(公告)号：US08324704B2

公开(公告)日：2012-12-04

申请号：US12659853

申请日：2010-03-23

申请人： Takeo Yamamoto ,  Takeshi Endo ,  Eiichi Okuno ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Takashi Katsuno ,  Yukihiko Watanabe

发明人： Takeo Yamamoto ,  Takeshi Endo ,  Eiichi Okuno ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Takashi Katsuno ,  Yukihiko Watanabe

IPC分类号： H01L29/24 ,  H01L29/47 ,  H01L21/04

CPC分类号： H01L29/47 ,  H01L21/0465 ,  H01L21/0495 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66143 ,  H01L29/872

摘要： A silicon carbide semiconductor device with a Schottky barrier diode includes a first conductivity type silicon carbide substrate, a first conductivity type silicon carbide drift layer on a first surface of the substrate, a Schottky electrode forming a Schottky contact with the drift layer, and an ohmic electrode on a second surface of the substrate. The Schottky electrode includes an oxide layer in direct contact with the drift layer. The oxide layer is made of an oxide of molybdenum, titanium, nickel, or an alloy of at least two of these elements.

摘要翻译： 具有肖特基势垒二极管的碳化硅半导体器件包括第一导电型碳化硅衬底，在衬底的第一表面上的第一导电型碳化硅漂移层，与漂移层形成肖特基接触的肖特基电极和欧姆 电极在基板的第二表面上。 肖特基电极包括与漂移层直接接触的氧化物层。 氧化物层由钼，钛，镍或这些元素中的至少两种的合金的氧化物制成。

公开(公告)号：US07825449B2

公开(公告)日：2010-11-02

申请号：US12289624

申请日：2008-10-30

申请人： Naohiro Suzuki ,  Yuuichi Takeuchi ,  Takeshi Endo ,  Eiichi Okuno ,  Toshimasa Yamamoto

发明人： Naohiro Suzuki ,  Yuuichi Takeuchi ,  Takeshi Endo ,  Eiichi Okuno ,  Toshimasa Yamamoto

IPC分类号： H01L29/94 ,  H01L21/04 ,  H01L29/68

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/7391 ,  H01L29/7397 ,  H01L29/7828

摘要： An SiC semiconductor device and a related manufacturing method are disclosed having a structure provided with a p+-type deep layer formed in a depth equal to or greater than that of a trench to cause a depletion layer between at a PN junction between the p+-type deep layer and an n−-type drift layer to extend into the n−-type drift layer in a remarkable length, making it difficult for a high voltage, resulting from an adverse affect arising from a drain voltage, to enter a gate oxide film. This results in a capability of minimizing an electric field concentration in the gate oxide film, i.e., an electric field concentration occurring at the gate oxide film at a bottom wall of the trench.

摘要翻译： 公开了一种SiC半导体器件和相关制造方法，其具有设置有等于或大于沟槽深度形成的p +型深层的结构，以在p +型之间的PN结处引起耗尽层 深层和n型漂移层以非常长的长度延伸到n型漂移层中，使得由于漏极电压引起的不利影响导致的高电压难以进入栅极氧化膜 。 这导致使栅极氧化膜中的电场浓度最小化的能力，即在沟槽的底壁处的栅极氧化膜处发生的电场浓度。