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12 条记录 (耗时 0.024 秒)

    Circuit board design aiding
    1.
    发明授权
    Circuit board design aiding 失效
    电路板设计辅助

    公开(公告)号：US06691296B1

    公开(公告)日：2004-02-10

    申请号：US09241946

    申请日：1999-02-01

    申请人： Takeshi Nakayama ,  Yukihiro Fukumoto ,  Yoshiyuki Saito ,  Hirokazu Uemura

    发明人： Takeshi Nakayama ,  Yukihiro Fukumoto ,  Yoshiyuki Saito ,  Hirokazu Uemura

    IPC分类号： G06F1750

    CPC分类号： H05K3/0005 ,  G06F17/5036 ,  G06F17/5072 ,  G06F17/5077 ,  H01L2924/15192 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/115 ,  H05K2201/10689

    摘要： A net detecting unit detects a set of component terminal interconnection information showing a critical net from a component terminal interconnection information list. A conductor detecting unit detects a conductor corresponding to the critical net. A component detecting unit detects two components from the set of component terminal interconnection information. A terminal detecting unit detects a power and/or ground terminal of each of the detected components. A power/ground layer detecting unit detects at least one layer, among power and ground layers, to which the detected power and/or ground terminals are connected. A layer detecting unit specifies a layer, among the detected layers, that is nearest to a signal layer on which the conductor is placed. A prohibition area generating unit generates a via prohibition area on the specified layer. As a result, vias are placed on the specified layer, avoiding the via prohibition area.

    摘要翻译： 网络检测单元从组件终端互连信息列表检测表示关键网络的一组组件终端互连信息。 导体检测单元检测与关键网相对应的导体。 分量检测单元从组件端子互连信息的集合中检测两个分量。 终端检测单元检测每个检测到的组件的功率和/或接地端子。 电源/接地层检测单元检测所连接的检测到的电力和/或接地端子的功率和接地层中的至少一层。 层检测单元指定在所检测的层之中最接近放置导体的信号层的层。 禁止区域生成单元在指定的层上生成通路禁止区域。 结果，通孔被放置在指定的层上，避免了通孔禁止区域。

    Circuit board design aiding apparatus, design aiding method, and storage medium storing design aiding program
    2.
    发明授权
    Circuit board design aiding apparatus, design aiding method, and storage medium storing design aiding program 有权
    电路板设计辅助设备，设计辅助方法和存储设备辅助程序存储介质

    公开(公告)号：US06629302B2

    公开(公告)日：2003-09-30

    申请号：US09746886

    申请日：2000-12-22

    申请人： Shinji Miura ,  Yukihiro Fukumoto ,  Hirokazu Uemura ,  Yoshiyuki Saito ,  Hiroshi Ikeda ,  Takeshi Nakayama ,  Osamu Shibata ,  Shinichi Tanimoto

    发明人： Shinji Miura ,  Yukihiro Fukumoto ,  Hirokazu Uemura ,  Yoshiyuki Saito ,  Hiroshi Ikeda ,  Takeshi Nakayama ,  Osamu Shibata ,  Shinichi Tanimoto

    IPC分类号： G06F945

    CPC分类号： G06F17/5068

    摘要： A design aiding apparatus and a method, and a storage medium storing a design aiding program enable the efficient layout design of components in a multilayer wiring board formed by laminating a plurality of wiring layers. The design aiding apparatus includes (a) a first acquiring unit for acquiring information showing a first location in a lamination direction of the wiring layers, (b) a second acquiring unit for acquiring information showing a second location on a two-dimensional plane that is orthogonal to the lamination direction, and (c) a placement unit for generating information showing a space to be occupied when the component is placed in such a manner that a placement reference point of the component coincides with the second location that is on the two-dimensional plane including the first location. According to the above construction, the present invention is capable of aiding layout design of components in the wiring board.

    摘要翻译： 设计辅助装置和方法以及存储设计辅助程序的存储介质使得能够通过层叠多个布线层而形成的多层布线板中的部件的有效布局设计。 设计辅助装置包括：（a）第一获取单元，用于获取表示布线层的层叠方向上的第一位置的信息，（b）第二获取单元，用于获取表示二维平面上的第二位置的信息， 与所述层叠方向正交，以及（c）放置单元，用于产生表示当所述部件以所述部件的放置基准点与所述第二位置的所述第二位置一致的方式配置时要占据的空间的信息， 包括第一位置的三维平面。 根据上述结构，本发明能够帮助布线板中部件的布局设计。

    Bidirectional signal transmission circuit and bus system
    4.
    发明授权
    Bidirectional signal transmission circuit and bus system 失效
    双向信号传输电路和总线系统

    公开(公告)号：US06812741B2

    公开(公告)日：2004-11-02

    申请号：US10394677

    申请日：2003-03-21

    申请人： Osamu Shibata ,  Yoshiyuki Saito ,  Yukihiro Fukumoto

    发明人： Osamu Shibata ,  Yoshiyuki Saito ,  Yukihiro Fukumoto

    IPC分类号： H03K190175

    CPC分类号： H04L25/0292 ,  G06F13/4086 ,  H04L5/16 ,  H04L25/0278 ,  H04L25/028

    摘要： A bidirectional transmission circuit for inputting/outputting a signal from/onto a bidirectional transmission line includes: a transceiver for transmitting/receiving a signal; a first element having an impedance; a second element being a short line; and a switching unit for coupling the transceiver to the bidirectional transmission line via the first element when the transceiver transmits a signal, and coupling the transceiver to the bidirectional transmission line via the second element when the transceiver receives a signal.

    摘要翻译： 用于从双向传输线路输入/输出信号的双向传输电路包括：用于发送/接收信号的收发器; 具有阻抗的第一元件; 第二个元素是短线; 以及切换单元，用于当收发器发送信号时，经由第一元件将收发器耦合到双向传输线，并且当收发器接收到信号时，将收发器经由第二元件耦合到双向传输线。

    Method, apparatus, and computer program for evaluating noise immunity of a semiconductor device
    7.
    发明授权
    Method, apparatus, and computer program for evaluating noise immunity of a semiconductor device 有权
    用于评估半导体器件的抗噪声性的方法，装置和计算机程序

    公开(公告)号：US07233889B2

    公开(公告)日：2007-06-19

    申请号：US10278507

    申请日：2002-10-23

    申请人： Eiji Takahashi ,  Yoshiyuki Saito ,  Yukihiro Fukumoto ,  Hiroshi Benno

    发明人： Eiji Takahashi ,  Yoshiyuki Saito ,  Yukihiro Fukumoto ,  Hiroshi Benno

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A method of evaluating noise immunity of a semiconductor device is provided. An actual circuit including the semiconductor device is represented by an equivalent circuit which has a target equivalent circuit, a noise source equivalent circuit, and an external equivalent circuit connected in parallel. The target equivalent circuit represents the semiconductor device. The noise source equivalent circuit represents a noise source outside the semiconductor device, and supplies noise to the target equivalent circuit. The external equivalent circuit represents a circuit outside the semiconductor device. The noise immunity is evaluated based on a voltage or current which arises in the target equivalent circuit by the noise. In this way, the immunity of the semiconductor device against extraneous noise can be evaluated in consideration of the effects of the circuitry outside the semiconductor device.

    摘要翻译： 提供了一种评估半导体器件的抗噪声性的方法。 包括半导体器件的实际电路由具有并联连接的目标等效电路，噪声源等效电路和外部等效电路的等效电路表示。 目标等效电路表示半导体器件。 噪声源等效电路表示半导体器件外部的噪声源，并且将噪声提供给目标等效电路。 外部等效电路表示半导体器件外部的电路。 基于由噪声在目标等效电路中产生的电压或电流来评估噪声抗扰度。 以这种方式，可以考虑半导体器件外的电路的影响来评估半导体器件对外来噪声的抗扰性。

    Power line carrier system
    9.
    发明授权
    Power line carrier system 有权
    电力线载波系统

    公开(公告)号：US07049939B2

    公开(公告)日：2006-05-23

    申请号：US10629803

    申请日：2003-07-30

    申请人： Hiroshi Ikeda ,  Yukihiro Fukumoto ,  Satoshi Hasako

    发明人： Hiroshi Ikeda ,  Yukihiro Fukumoto ,  Satoshi Hasako

    IPC分类号： H04M11/04

    CPC分类号： H04B3/54 ,  H04B2203/5445 ,  H04B2203/5454

    摘要： The power line carrier system provides with a filter in a power branch apparatus removable from an external power line. The filter passes a power line carrier signal in a signal mode for the external power line, and interrupts another power line carrier signal which is in a signal mode different from the mode for the external power line.

    摘要翻译： 电力线载波系统在可从外部电力线路移除的动力分支装置中提供过滤器。 滤波器以外部电力线的信号模式通过电力线载波信号，并且中断与外部电力线的模式不同的信号模式的另一个电力线载波信号。