公开(公告)号：US06235632B1

公开(公告)日：2001-05-22

申请号：US09006495

申请日：1998-01-13

申请人： Takeshi Nogami ,  Guarionex Morales ,  Minh Van Ngo

发明人： Takeshi Nogami ,  Guarionex Morales ,  Minh Van Ngo

IPC分类号： H01L2144

CPC分类号： H01L21/76864 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76895

摘要： In a preferred embodiment, there is disclosed a method of forming a tungsten plug at the via level. A metal line is formed in a top portion of a first insulating layer. A second insulating layer is formed on the first insulating layer and over an exposed surface of the metal line. An etching process is applied to a region of the second insulating layer formed over the exposed surface of the metal line to create a contact hole within the region. The metal line is exposed at the region. A tungsten nitride thin film is deposited over the second insulating layer and the exposed metal line. A blanket tungsten thin film is deposited to fill the contact hole and to form a planar layer successively to the depositing of the tungsten nitride thin film. The tungsten nitride thin film and the blanket tungsten thin film are chemically mechanically polished until the upper surface of the second insulating layer is exposed.

摘要翻译： 在优选实施例中，公开了一种在通孔级形成钨丝塞的方法。 金属线形成在第一绝缘层的顶部。 在第一绝缘层上和金属线的暴露表面上形成第二绝缘层。 对形成在金属线的暴露表面上的第二绝缘层的区域施加蚀刻处理，以在该区域内形成接触孔。 金属线暴露在该地区。 在第二绝缘层和暴露的金属线上沉积氮化钨薄膜。 沉积覆盖的钨薄膜以填充接触孔并且连续地形成平坦层以沉积氮化钨薄膜。 化学机械抛光氮化钨薄膜和覆盖钨薄膜，直到第二绝缘层的上表面露出。

公开(公告)号：US06033584A

公开(公告)日：2000-03-07

申请号：US995499

申请日：1997-12-22

申请人： Minh Van Ngo ,  Guarionex Morales ,  Takeshi Nogami

发明人： Minh Van Ngo ,  Guarionex Morales ,  Takeshi Nogami

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/31122 ,  H01L21/76838

摘要： A method of integrated circuit fabrication creating copper interconnect structures wherein the formation of copper oxide is reduced or eliminated by etching away the copper oxide performing an H.sub.2 plasma treatment in a plasma enhanced chemical vapor deposition chamber.

摘要翻译： 一种形成铜互连结构的集成电路制造方法，其中通过在等离子体增强化学气相沉积室中蚀刻掉执行H 2等离子体处理的氧化铜来减少或消除氧化铜的形成。

公开(公告)号：US06281584B1

公开(公告)日：2001-08-28

申请号：US09373482

申请日：1999-08-12

申请人： Minh Van Ngo ,  Richard J. Huang ,  Guarionex Morales

发明人： Minh Van Ngo ,  Richard J. Huang ,  Guarionex Morales

IPC分类号： H01L2348

CPC分类号： H01L21/31629 ,  H01L21/76801 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.

摘要翻译： 一种在制造半导体产品的方法中使用低电介质SiOF的方法，包括以下步骤：获得SiOF层，并从SiOF层的表面上消耗氟。 在优选的实施方案中，耗尽步骤包括用含有氨的等离子体处理SiOF层的表面的步骤。 进一步优选的是，经过处理的表面被亚硝酸盐等离子体钝化。 本发明还包括半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中SiOF电介质层包括其一个边缘处的第一区域，该第一区域耗尽氟 到预定深度。

公开(公告)号：US06444593B1

公开(公告)日：2002-09-03

申请号：US09373483

申请日：1999-08-12

申请人： Minh Van Ngo ,  Richard J. Huang ,  Guarionex Morales

发明人： Minh Van Ngo ,  Richard J. Huang ,  Guarionex Morales

IPC分类号： H01L21425

CPC分类号： H01L21/31629 ,  H01L21/02131 ,  H01L21/02274 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which depleted of fluorine to a predetermined depth.

摘要翻译： 一种在制造半导体产品的方法中使用低电介质SiOF的方法，包括以下步骤：获得SiOF层，并从SiOF层的表面上消耗氟。 在优选的实施方案中，耗尽步骤包括用含有氨的等离子体处理SiOF层的表面的步骤。 进一步优选的是，经过处理的表面被亚硝酸盐等离子体钝化。 本发明还包括半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中所述SiOF电介质层包括其一个边缘处的第一区域，所述第一区域耗尽氟至 预定深度。

公开(公告)号：US06660634B1

公开(公告)日：2003-12-09

申请号：US10291612

申请日：2002-11-12

申请人： Minh Van Ngo ,  Shekhar Pramanick ,  Takeshi Nogami

发明人： Minh Van Ngo ,  Shekhar Pramanick ,  Takeshi Nogami

IPC分类号： H01L2144

CPC分类号： H01L21/76862 ,  H01L21/76801 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10S438/902 ,  Y10S438/906 ,  H01L2924/00

摘要： The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) under plasma conditions with ammonia and silane or dichlorosilane to form a copper silicide layer thereon; or (b) with an ammonia plasma followed by reaction with silane or dichlorosilane to form a copper silicide layer thereon. The diffusion barrier layer is then deposited on the copper silicide layer. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, then treating the exposed surface of the Cu/Cu alloy interconnect to form the copper silicide layer thereon, and depositing a silicon nitride diffusion barrier layer on the copper silicide layer.

摘要翻译： 扩散阻挡层或覆盖层对Cu或Cu合金互连构件的粘附通过处理Cu或Cu合金互连构件的暴露表面而显着增强：（a）在等离子体条件下用氨和硅烷或二氯硅烷形成铜 硅化物层; 或（b）与氨等离子体接触，然后与硅烷或二氯硅烷反应，在其上形成硅化铜层。 然后将扩散阻挡层沉积在硅化铜层上。 实施例包括电镀或化学镀Cu或Cu合金以填充介电中间层中的镶嵌开口，化学机械抛光，然后处理Cu / Cu合金互连的暴露表面以在其上形成硅化铜层，并沉积氮化硅 扩散阻挡层在硅化铜层上。

公开(公告)号：US06472755B1

公开(公告)日：2002-10-29

申请号：US09688928

申请日：2000-10-17

申请人： Minh Van Ngo ,  Takeshi Nogami

发明人： Minh Van Ngo ,  Takeshi Nogami

IPC分类号： H01L2348

CPC分类号： H01L23/53238 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

摘要： Cu diffusion between Cu and Cu alloy interconnect members, e.g., lines, in a silicon oxide inter-layer dielectric is avoided or substantially reduced by converting an upper portion of the silicon oxide inter-layer dielectric between neighboring lines to silicon oxynitride and then depositing a capping layer. Embodiments include filling damascene trenches in a silicon oxide inter-layer dielectric with Cu or a Cu alloy, CMP to effect planarization such that the upper surfaces of the lines are substantially coplanar with the upper surface of the inter-layer dielectric and treating the exposed surfaces with a high strength ammonia plasma to ion bombard the exposed inter line silicon oxide with nitrogen atoms, thereby converting the upper portion to silicon oxynitride, while simultaneously removing or substantially reducing surface oxides on the lines. A silicon nitride capping layer is then deposited.

摘要翻译： 通过将相邻线路之间的氧化硅层间电介质的上部部分转换为氮氧化硅，然后沉积氧化硅层，从而避免或基本上减少氧化硅层间电介质中Cu和Cu合金互连构件（例如线）之间的Cu扩散 盖层 实施例包括用Cu或Cu合金填充氧化硅层间电介质中的镶嵌沟槽CMP，以实现平面化，使得线的上表面与层间电介质的上表面基本上共面并且处理暴露表面 用高强度氨等离子体离子轰击具有氮原子的暴露的线间氧化硅，从而将上部转化为氮氧化硅，同时除去或显着还原线上的表面氧化物。 然后沉积氮化硅覆盖层。

公开(公告)号：US06335283B1

公开(公告)日：2002-01-01

申请号：US09477719

申请日：2000-01-05

申请人： Minh Van Ngo ,  Takeshi Nogami

发明人： Minh Van Ngo ,  Takeshi Nogami

IPC分类号： H01L2144

CPC分类号： H01L21/76834 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76883

摘要： Cu diffusion between Cu and Cu alloy interconnect members, e.g., lines, in a silicon oxide inter-layer dielectric is avoided or substantially reduced by converting an upper portion of the silicon oxide inter-layer dielectric between neighboring lines to silicon oxynitride and then depositing a capping layer. Embodiments include filling damascene trenches in a silicon oxide inter-layer dielectric with Cu or a Cu alloy, CMP to effect planarization such that the upper surfaces of the lines are substantially coplanar with the upper surface of the inter-layer dielectric and treating the exposed surfaces with a nitrogen plasma of sufficient strength to ion bombard the exposed inter line silicon oxide with nitrogen, thereby converting the upper portion to silicon oxynitride, while simultaneously removing or substantially reducing surface oxides on the lines. A silicon nitride capping layer is then deposited.

摘要翻译： 通过将相邻线路之间的氧化硅层间电介质的上部部分转换为氮氧化硅，然后沉积氧化硅层，从而避免或基本上减少氧化硅层间电介质中Cu和Cu合金互连构件（例如线）之间的Cu扩散 盖层 实施例包括用Cu或Cu合金填充氧化硅层间电介质中的镶嵌沟槽CMP，以实现平面化，使得线的上表面与层间电介质的上表面基本上共面并且处理暴露表面 具有足够强度的氮等离子体用氮气轰击暴露的线间氧化硅，从而将上部部分转化为氮氧化硅，同时除去或基本上还原管线上的表面氧化物。 然后沉积氮化硅覆盖层。

公开(公告)号：US06303505B1

公开(公告)日：2001-10-16

申请号：US09112472

申请日：1998-07-09

申请人： Minh Van Ngo ,  Shekhar Pramanick ,  Takeshi Nogami

发明人： Minh Van Ngo ,  Shekhar Pramanick ,  Takeshi Nogami

IPC分类号： H01L2144

CPC分类号： H01L21/76849 ,  H01L21/76838 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Capping layer adhesion to a Cu or Cu alloy interconnect member is enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member with a hydrogen plasma to substantially reduce oxides thereon, forming a thin layer of copper silicide on the treated surface and depositing the capping layer thereon. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric layer, chemical-mechianiical polishing, hydrogen plasma treatment, reacting the treated surface with silane or dichlorosilane to form a layer of copper silicide on the treated surface and depositing a silicon nitride capping layer on the thin copper silicide layer.

摘要翻译： 通过用氢等离子体处理Cu或Cu合金互连构件的暴露表面以大大减少其上的氧化物，在处理过的表面上形成薄的硅化铜层，并沉积到Cu或Cu合金互连构件上， 盖层。 实施例包括电镀或化学镀Cu或Cu合金以填充电介质层中的镶嵌开口，化学机械抛光，氢等离子体处理，使经处理的表面与硅烷或二氯硅烷反应，以在被处理的表面上形成硅化铜层， 在薄的硅化铜层上沉积氮化硅覆盖层。

公开(公告)号：US06211084B1

公开(公告)日：2001-04-03

申请号：US09112161

申请日：1998-07-09

申请人： Minh Van Ngo ,  Shekhar Pramanick ,  Takeshi Nogami

发明人： Minh Van Ngo ,  Shekhar Pramanick ,  Takeshi Nogami

IPC分类号： H01L2144

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The adhesion of a diffusion barrier or capping layer to Cu and/or Cu alloy interconnect members is significantly enhanced by treating the exposed surface of the Cu and/or Cu alloy interconnect members with a silane or dichlorosilane plasma to form a layer of copper silicide thereon prior to depositing the capping layer. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, treating the exposed surface of the Cu or Cu alloy interconnect member in a silane or dichlorosilane plasma to form the copper silicide layer and depositing a capping layer of silicon nitride thereon.

摘要翻译： 通过用硅烷或二氯硅烷等离子体处理Cu和/或Cu合金互连构件的暴露表面以在其上形成硅化铜层，扩散阻挡层或覆盖层对Cu和/或Cu合金互连构件的粘附性显着增强 在沉积覆盖层之前。 实施例包括电镀或化学镀Cu或Cu合金以填充介电中间层中的镶嵌开口，化学机械抛光，处理硅烷或二氯硅烷等离子体中Cu或Cu合金互连构件的暴露表面以形成硅化铜层和 在其上沉积氮化硅覆盖层。

公开(公告)号：US06214731B1

公开(公告)日：2001-04-10

申请号：US09442771

申请日：1999-11-18

申请人： Takeshi Nogami ,  Minh Van Ngo ,  Shekhar Pramanick

发明人： Takeshi Nogami ,  Minh Van Ngo ,  Shekhar Pramanick

IPC分类号： H01L2144

CPC分类号： H01L21/76856 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Cu interconnection patterns with improved electromigration resistance are formed by depositing a barrier metal layer, such as W or WN, to line an opening in a dielectric layer. The exposed surface of the deposited barrier metal layer is treated with silane or dichlorosaline to form a thin silicon layer thereon. Cu is then deposited to fill the opening and reacted with the thin silicon layer to form a thin layer of Cu silicide at the interface between Cu and the barrier metal layer, thereby reducing the interface defect density and improving electromigration resistance.

摘要翻译： 具有改善的电迁移电阻的Cu互连图案通过沉积阻挡金属层（例如W或WN）来形成，以对电介质层中的开口进行排列。 沉积的阻挡金属层的暴露表面用硅烷或二氯苯胺处理以在其上形成薄硅层。 然后沉积Cu以填充开口并与薄硅层反应以在Cu和阻挡金属层之间的界面处形成Cu硅化物的薄层，从而降低界面缺陷密度并提高电迁移阻力。