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238 条记录 (耗时 0.037 秒)

    Method of resource arbitration
    2.
    发明授权
    Method of resource arbitration 失效
    资源仲裁方法

    公开(公告)号：US07099975B2

    公开(公告)日：2006-08-29

    申请号：US10730952

    申请日：2003-12-09

    申请人： Jeffrey Douglas Brown ,  Scott Douglas Clark ,  Charles Ray Johns ,  Takeshi Yamazaki

    发明人： Jeffrey Douglas Brown ,  Scott Douglas Clark ,  Charles Ray Johns ,  Takeshi Yamazaki

    IPC分类号： G06F12/00

    CPC分类号： G06F13/3625

    摘要： An improved method and apparatus for resource arbitration. Four priority classes, managed high (MH), managed low (ML), opportunistic high (OH) and opportunistic low (OL), are defined. A priority class is assigned to each resource access request. An access request concentrator (ARC) is created for each resource, through which the resource is accessed. An access request is chosen at each ARC using the priority order MH, ML, OH, and OL, in decreasing order of priority. If OH priority class resource access requests are locked out, the priority order is temporarily changed to OH, OL, MH, and ML, in decreasing order of priority. If OL priority class resource access requests are locked out, the priority order is temporarily changed to MH, OL, OH, and ML, in decreasing order of priority.

    摘要翻译： 一种改进的资源仲裁方法和装置。 定义了四个优先级，管理高（MH），管理低（ML），机会高（OH）和机会主义低（OL）。 优先级分配给每个资源访问请求。 为每个资源创建访问请求集中器（ARC），通过该资源访问资源。 在优先级顺序为MH，ML，OH和OL的每个ARC中选择访问请求。 如果OH优先级资源访问请求被锁定，优先级顺序将按照优先级的降序暂时更改为OH，OL，MH和ML。 如果OL优先级资源访问请求被锁定，优先级顺序将按照优先级的降序临时更改为MH，OL，OH和ML。

    Microprocessor having bandwidth management for computing applications and related method of managing bandwidth allocation
    6.
    发明授权
    Microprocessor having bandwidth management for computing applications and related method of managing bandwidth allocation 失效
    具有用于计算应用的带宽管理的微处理器和管理带宽分配的相关方法

    公开(公告)号：US07107363B2

    公开(公告)日：2006-09-12

    申请号：US10464882

    申请日：2003-06-19

    申请人： Jeffrey Douglas Brown ,  Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Takeshi Yamazaki

    发明人： Jeffrey Douglas Brown ,  Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Takeshi Yamazaki

    IPC分类号： G06F3/00

    CPC分类号： G06F9/5011 ,  G06F2209/5014

    摘要： The present invention discloses, in one aspect, a microprocessor. In one embodiment, the microprocessor includes a processing element configured to process an application using a bandwidth. The microprocessor also includes an access shaper coupled to the processing element and configured to shape storage requests for the processing of the application. In this embodiment, the microprocessor further includes bandwidth management circuitry coupled to the access shaper and configured to track the bandwidth usage based on the requests. A method of coordinating bandwidth allocation and a processor assembly are also disclosed.

    摘要翻译： 本发明在一个方面公开了一种微处理器。 在一个实施例中，微处理器包括被配置为使用带宽来处理应用的处理元件。 微处理器还包括一个接入整形器，它与处理元件相耦合，并配置成形成用于处理应用的存储请求。 在该实施例中，微处理器还包括耦合到接入整形器的带宽管理电路，并且被配置为基于请求跟踪带宽使用。 还公开了一种协调带宽分配的方法和处理器组件。

    Resource dedication system and method for a computer architecture for broadband networks
    8.
    发明授权
    Resource dedication system and method for a computer architecture for broadband networks 有权
    宽带网络计算机架构的资源投入系统和方法

    公开(公告)号：US06809734B2

    公开(公告)日：2004-10-26

    申请号：US09815558

    申请日：2001-03-22

    申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Charles Ray Johns ,  Shigehiro Asano ,  Atsushi Kunimatsu ,  Yukio Watanabe

    发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Charles Ray Johns ,  Shigehiro Asano ,  Atsushi Kunimatsu ,  Yukio Watanabe

    IPC分类号： G06T120

    CPC分类号： G06F9/4893 ,  A63F2300/20 ,  A63F2300/538 ,  Y02D10/24

    摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

    摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。 还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

    Establishing command order in an out of order DMA command queue
    9.
    发明授权
    Establishing command order in an out of order DMA command queue 失效
    在命令行DMA命令队列中建立命令顺序

    公开(公告)号：US07243200B2

    公开(公告)日：2007-07-10

    申请号：US10891772

    申请日：2004-07-15

    申请人： Michael Norman Day ,  Charles Ray Johns ,  Peichun Peter Liu ,  Thuong Truong ,  Takeshi Yamazaki

    发明人： Michael Norman Day ,  Charles Ray Johns ,  Peichun Peter Liu ,  Thuong Truong ,  Takeshi Yamazaki

    IPC分类号： G06F12/00

    CPC分类号： G06F13/28

    摘要： A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.

    摘要翻译： 提供了一种用于控制存储器访问的方法，装置和计算机程序。 直接存储器访问（DMA）单元已经在许多总线架构中变得普遍。 然而，管理有限的系统资源已成为多个DMA单元的挑战。 为了管理生成的多个命令并保留依赖关系，使用命令中的嵌入式标志或障碍命令。 这些操作然后可以控制执行命令的顺序，以便保留依赖性。

    Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment
    10.
    发明授权
    Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment 有权
    非对称异构多处理器环境中的内存障碍原语

    公开(公告)号：US07725618B2

    公开(公告)日：2010-05-25

    申请号：US10902474

    申请日：2004-07-29

    申请人： Michael Norman Day ,  Charles Ray Johns ,  Peichun Peter Liu ,  Thuong Truong ,  Takeshi Yamazaki

    发明人： Michael Norman Day ,  Charles Ray Johns ,  Peichun Peter Liu ,  Thuong Truong ,  Takeshi Yamazaki

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.

    摘要翻译： 本发明提供了一种用于在直接存储器访问（DMA）设备中创建存储障碍的方法和装置。 接收到存储器屏障命令并接收存储器命令。 内存命令是根据内存屏障命令执行的。 基于内存障碍命令启动总线操作。 基于总线操作接收总线操作确认。 基于总线操作确认执行存储器障碍命令。 在特定方面，存储器屏障命令是直接存储器访问同步（dmasync），并且直接存储器访问强制执行输入/输出（dmaeie））命令的按顺序执行。