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公开(公告)号：US07700997B2
公开(公告)日：2010-04-20
申请号：US11346293
申请日：2006-02-03
申请人： Takuya Futatsuyama , Toshiya Kotani , Hiromitsu Mashita , Atsushi Maesono , Ayako Nakano , Tadahito Fujisawa
发明人： Takuya Futatsuyama , Toshiya Kotani , Hiromitsu Mashita , Atsushi Maesono , Ayako Nakano , Tadahito Fujisawa
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , H01L27/11517
摘要： According to this invention, the NAND type flash memory of high reliability is realized. It provides a semiconductor memory device comprising: a plurality of memory cells; a plurality of word lines formed by a first gate wiring layer; a plurality of first transistors for providing voltages to said word lines; and electrical connections for connection said word lines and sources or drains of said first transistors, said electrical connections being formed of both first wirings of a first wiring layer formed above said first gate wiring layer and second wirings of a second wiring layers formed above said first wiring layer.
摘要翻译： 根据本发明，实现了高可靠性的NAND型闪速存储器。 它提供一种半导体存储器件，包括：多个存储单元; 由第一栅极布线层形成的多个字线; 用于向所述字线提供电压的多个第一晶体管; 以及用于连接所述字线和所述第一晶体管的源极或漏极的电连接，所述电连接由形成在所述第一栅极布线层上方的第一布线层的第一布线和形成在所述第一晶体管上方的第二布线层的第二布线形成 接线层。
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公开(公告)号：US20060197136A1
公开(公告)日：2006-09-07
申请号：US11346293
申请日：2006-02-03
申请人： Takuya Futatsuyama , Toshiya Kotani , Hiromitsu Mashita , Atsushi Maesono , Ayako Nakano , Tadahito Fujisawa
发明人： Takuya Futatsuyama , Toshiya Kotani , Hiromitsu Mashita , Atsushi Maesono , Ayako Nakano , Tadahito Fujisawa
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11517
摘要： According to this invention, the NAND type flash memory of high reliability is realized. It provides a semiconductor memory device comprising: a plurality of memory cells; a plurality of word lines formed by a first gate wiring layer; a plurality of first transistors for providing voltages to said word lines; and electrical connections for connection said word lines and sources or drains of said first transistors, said electrical connections being formed of both first wirings of a first wiring layer formed above said first gate wiring layer and second wirings of a second wiring layers formed above said first wiring layer.
摘要翻译： 根据本发明，实现了高可靠性的NAND型闪速存储器。 它提供一种半导体存储器件，包括：多个存储单元; 由第一栅极布线层形成的多个字线; 用于向所述字线提供电压的多个第一晶体管; 以及用于连接所述字线和所述第一晶体管的源极或漏极的电连接，所述电连接由形成在所述第一栅极布线层上方的第一布线层的第一布线和形成在所述第一晶体管上方的第二布线层的第二布线形成 接线层。
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公开(公告)号：US20100264547A1
公开(公告)日：2010-10-21
申请号：US12774160
申请日：2010-05-05
IPC分类号： H01L23/52 , H01L23/544
CPC分类号： G11C5/02 , G11C5/063 , H01L27/105 , H01L27/115 , H01L27/11573
摘要： A first region having a first metal wiring, the first metal wiring being buried into an insulation film with a first minimum dimension, and a second region having a second metal wiring, the second metal wiring being buried in the insulation film with a second minimum dimension which is larger than the first minimum dimension, the second region being arranged adjacent to the first region, wherein a thickness of the first metal wiring and a thickness of the second metal wiring are different.
摘要翻译： 具有第一金属布线的第一区域，所述第一金属布线被掩埋在具有第一最小尺寸的绝缘膜中，所述第二区域具有第二金属布线，所述第二金属布线以第二最小尺寸被掩埋在所述绝缘膜中 其大于第一最小尺寸，第二区域布置成与第一区域相邻，其中第一金属布线的厚度和第二金属布线的厚度不同。
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公开(公告)号：US20090014841A1
公开(公告)日：2009-01-15
申请号：US12169270
申请日：2008-07-08
CPC分类号： G11C5/02 , H01L27/105 , H01L27/115 , H01L27/11526
摘要： A first region having a first pattern which includes a first minimum dimension, a second region having a second pattern which includes a second minimum dimension larger the first minimum dimension, the second region being arranged adjacent to the first region, wherein a boundary between the first region and the second region is sectioned by a width which is twice of more of a minimum dimension which exists in an adjacent region.
摘要翻译： 具有包括第一最小尺寸的第一图案的第一区域，具有第二图案的第二区域，所述第二图案包括具有大于所述第一最小尺寸的第二最小尺寸，所述第二区域布置成与所述第一区域相邻，其中所述第一图案 区域，并且第二区域被存在于相邻区域中的最小尺寸的两倍以上的宽度分割。
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公开(公告)号：US07738276B2
公开(公告)日：2010-06-15
申请号：US12169270
申请日：2008-07-08
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , H01L27/105 , H01L27/115 , H01L27/11526
摘要： A first region having a first pattern which includes a first minimum dimension, a second region having a second pattern which includes a second minimum dimension larger the first minimum dimension, the second region being arranged adjacent to the first region, wherein a boundary between the first region and the second region is sectioned by a width which is twice of more of a minimum dimension which exists in an adjacent region.
摘要翻译： 具有包括第一最小尺寸的第一图案的第一区域，具有第二图案的第二区域，所述第二图案包括具有大于所述第一最小尺寸的第二最小尺寸，所述第二区域布置成与所述第一区域相邻，其中所述第一图案 区域，并且第二区域被存在于相邻区域中的最小尺寸的两倍以上的宽度分割。
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公开(公告)号：US08605503B2
公开(公告)日：2013-12-10
申请号：US13711894
申请日：2012-12-12
申请人： Takuya Futatsuyama
发明人： Takuya Futatsuyama
CPC分类号： G06F3/061 , G06F3/0619 , G06F3/0652 , G06F3/0656 , G06F3/0679 , G06F3/0688 , G11C11/5628 , G11C16/0408 , G11C16/045 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C2211/5648
摘要： A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.
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公开(公告)号：US08565020B2
公开(公告)日：2013-10-22
申请号：US13053796
申请日：2011-03-22
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3436
摘要： A memory includes word lines, bit lines, memory cells each having a gate connected to one of the word lines, a word line driver configured to drive voltages of the word lines, and a sense amplifier configured to detect data of the memory cells via the bit lines. The memory cells are connected in series between the bit lines and a source to constitute cell string. The word line driver increases a verification voltage of any of non-selected word lines connected to non-selected memory cells in the cell string at a time of a verify operation in a certain writing loop of a writing stage. The writing stage includes a plurality of writing loops. The writing loops respectively includes a write operation to write data in a selected memory cell in the cell string and a verify operation to verify that the data are written in the selected memory cell.
摘要翻译： 存储器包括字线，位线，各自具有连接到字线之一的栅极的存储单元，配置为驱动字线的电压的字线驱动器，以及经配置以经由该行线检测存储器单元的数据的读出放大器 位线。 存储单元串联在位线和源之间以构成单元串。 在写入阶段的某个写入循环中，在验证操作时，字线驱动器增加连接到单元串中未选择的存储单元的任何未选择字线的验证电压。 写入阶段包括多个写入循环。 写入循环分别包括写入操作以在单元串中的选定的存储单元中写入数据，以及验证操作以验证数据被写入所选存储单元。
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公开(公告)号：US08203885B2
公开(公告)日：2012-06-19
申请号：US13178718
申请日：2011-07-08
申请人： Naofumi Abiko , Takuya Futatsuyama
发明人： Naofumi Abiko , Takuya Futatsuyama
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C2211/5621 , G11C2211/5634 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： According to an embodiment, a nonvolatile semiconductor memory system includes: a nonvolatile semiconductor memory; and a memory controller having: a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory; a memory that stores writing information indicating a memory cell transistor that is written the latest in each of the NAND cell units; and a processor that sets a read voltage based on the writing information to read out data from the memory cell transistors connected to a first word line; wherein a row controller is configured to set a plurality of levels of the read voltage to be applied to the first word line, with respect to one threshold for discriminating data stored in a memory cell transistors.
摘要翻译： 根据实施例，非易失性半导体存储器系统包括：非易失性半导体存储器; 以及存储器控制器，具有：存储器接口单元，其向非易失性半导体存储器输入命令并在非易失性半导体存储器之间输入或输出数据; 存储器，其存储表示在每个NAND单元单元中写入最新的存储单元晶体管的写入信息; 以及处理器，其基于写入信息设置读取电压，以从连接到第一字线的存储单元晶体管读出数据; 其中行控制器被配置为相对于用于识别存储在存储单元晶体管中的数据的一个阈值来设置要施加到第一字线的读取电压的多个电平。
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公开(公告)号：US20110216593A1
公开(公告)日：2011-09-08
申请号：US13108641
申请日：2011-05-16
IPC分类号： G11C16/04
CPC分类号： G11C16/08 , G11C8/08 , G11C16/0483
摘要： A method of controlling a programming of a flash memory with memory blocks. The method includes checking whether a selected block among the memory blocks belongs to a first group or a second group. The method further includes executing the programming from a least bit address when the selected block belongs to the first group. The method also includes executing the programming from a most bit address when the selected block belongs to the second group.
摘要翻译： 一种利用存储块控制闪速存储器编程的方法。 该方法包括检查存储器块中的所选块是否属于第一组或第二组。 该方法还包括当所选择的块属于第一组时从最小位地址执行编程。 该方法还包括当所选择的块属于第二组时从大多数位地址执行编程。
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公开(公告)号：US07889537B2
公开(公告)日：2011-02-15
申请号：US12118064
申请日：2008-05-09
申请人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
发明人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/32 , G11C2213/72
摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.
摘要翻译： 本发明提供一种将数据写入非易失性存储器件的方法，该非易失性存储器件具有彼此相交的第一布线和第二布线以及布置在其间的每个交叉处的存储单元，每个存储单元具有可变电阻元件和整流元件 系列。 根据该方法，在所选择的第一布线中升高之前，将第二布线充电至不小于整流元件阈值的一定电压。 然后，将所选择的第一布线充电到写入或擦除所需的电压，之后放电所选择的第二布线。
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