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公开(公告)号：US06911692B2
公开(公告)日：2005-06-28
申请号：US10646590
申请日：2003-08-22
IPC分类号： H01L23/29 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/739 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7802 , H01L23/293 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/402 , H01L29/404 , H01L29/4238 , H01L29/7395 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A MOS semiconductor device includes n−-type surface regions, which are extended portions of an n−-type drift layer 12 extended to the surface of the semiconductor chip. Each n−-type surface region 14 is shaped with a stripe surrounded by a p-type well region. The surface area ratio between n−-type surface regions 14 and p-type well region 13 including an n+-type region 15 is from 0.01 to 0.2. The MOS semiconductor device further includes, in the breakdown withstanding region thereof, a plurality of guard rings, the number of which is equal to or more than the number n calculated from the following equation n=(Breakdown voltage Vbr (V))/100, and the spacing between the adjacent guard rings is set at 1 μm or less.
摘要翻译： 一种MOS半导体器件包括n + O - 型表面区域，其是延伸到半导体芯片的表面的n + O - 型漂移层12的延伸部分。 每一个n型 - 表面区域14成形为由p型阱区域围绕的条纹。 包括n + +型区域15在内的n + - 型表面区域14和p型阱区域13之间的表面积比为0.01〜0.2。 MOS半导体器件在其击穿区域中进一步包括多个保护环，其数量等于或大于根据以下等式计算的数n：n =（击穿电压Vbr（V））/ 100 ，相邻保护环之间的间隔设定为1um以下。
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公开(公告)号：US06943410B2
公开(公告)日：2005-09-13
申请号：US10170216
申请日：2002-06-12
IPC分类号： H01L29/06 , H01L29/08 , H01L29/423 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L23/58
CPC分类号： H01L29/7802 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/0847 , H01L29/402 , H01L29/4238 , H01L2924/0002 , H01L2924/00
摘要： A vertical MOS semiconductor device exhibits a high breakdown voltage and low on-resistance, reduces the tradeoff relation between the on-resistance and the breakdown voltage, and realizes high speed switching. The semiconductor device has a breakdown-voltage sustaining layer, such as an n−-type drift layer, and a well region, such as a p-type well region, in the breakdown-voltage sustaining layer. The resistivity ρ (Ωcm) of the breakdown-voltage layer is within a range expressed in terms of the breakdown voltage Vbr (V). The semiconductor device also has stripe shaped surface drain regions that extend from the well region and are surrounded by the well region. The surface area ratio between surface drain regions and the well region, which includes the source region, is from 0.01 to 0.2.
摘要翻译： 垂直MOS半导体器件表现出高的击穿电压和低导通电阻，降低了导通电阻和击穿电压之间的折衷关系，实现了高速切换。 该半导体器件具有击穿电压维持层，例如n + P型漂移层，以及击穿电压维持层中的诸如p型阱区的阱区。 击穿电压层的电阻率rho（Ωgacm）在以击穿电压Vbr（V）表示的范围内。 半导体器件还具有从阱区域延伸并被阱区域包围的条形表面漏极区域。 表面漏区与包含源区的阱区的表面积比为0.01〜0.2。
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公开(公告)号：US06894319B2
公开(公告)日：2005-05-17
申请号：US10020573
申请日：2001-10-31
IPC分类号： H01L23/29 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7802 , H01L23/293 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/402 , H01L29/404 , H01L29/4238 , H01L29/7395 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A MOS semiconductor device includes n−-type surface regions, which are extended portions of an n−-type drift layer 12 extended to the surface of the semiconductor chip. Each n−-type surface region 14 is shaped with a stripe surrounded by a p-type well region. The surface area ratio between n−-type surface regions 14 and p-type well region 13 including an n+-type region 15 is from 0.01 to 0.2. The MOS semiconductor device further includes, in the breakdown withstanding region thereof, a plurality of guard rings, the number of which is equal to or more than the number n calculated from the following equation n=(Breakdown voltage Vbr (V))/100, and the spacing between the adjacent guard rings is set at 1 μm or less.
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公开(公告)号：US5990518A
公开(公告)日：1999-11-23
申请号：US164487
申请日：1998-10-01
IPC分类号： H01L21/336 , H01L29/06 , H01L29/10 , H01L29/739 , H01L29/78 , H01L29/76
CPC分类号： H01L29/1095 , H01L29/7802 , H01L29/0696
摘要： An n.sup.+ drain layer 2 and an n.sup.- layer 1 on n.sup.+ drain layer 2 constitute a substrate for the semiconductor arrangement. A p-type base region 3 is in the surface portion of n.sup.- layer 1. An n.sup.+ source region 6 is formed in the surface portion of p-type base region 3. A p.sup.+ region 5, deeper than n.sup.+ source region 6 and shallower than p-type base region 3, partially overlaps n.sup.+ source region 6 and extends thoroughly into the portion of p-type base region 3 surrounded by n.sup.+ source region 6. A channel portion 7 is in the surface portion of p-type base region 3 extending between n.sup.- layer 1 and n.sup.+ source regions 6. A gate electrode 8 is disposed above channel portion 7 with a gate insulation film 9 interposed therebetween. A source electrode 11 contacts with p.sup.+ region 5 and n.sup.+ source region 6. An inter-layer insulation film 10 on gate electrode 8 insulates source electrode 11 from gate electrode 8. A drain electrode 12 is on the surface of n.sup.+ drain layer 2. A junction face 20 of p-type base region 3 and n.sup.- layer 1 has a finite radius of curvature such that the depth from the surface of p.sup.+ region 5 to junction face 20 is deepest beneath the center of p.sup.+ region 5.
摘要翻译： n +漏极层2上的n +漏极层2和n层1构成用于半导体装置的衬底。 p型基极区域3在n层1的表面部分中。在p型基极区域3的表面部分中形成n +源极区域6.比n +源极区域6更深的p +区域5 比p型基极区域3部分地重叠n +源极区域6，并且充分地延伸到由n +源极区域6包围的p型基极区域3的部分中。沟道部分7在p型基极区域3的表面部分中 在n层1和n +源极区域6之间延伸。栅极电极8设置在通道部分7之上，栅极绝缘膜9插入其间。 源极电极11与p +区域5和n +源极区域6接触。栅电极8上的层间绝缘膜10使源电极11与栅电极8绝缘。漏电极12在n +漏极层2的表面上。 p型基极区域3和n层1的接合面20具有有限的曲率半径，使得从p +区域5的表面到结面20的深度最深在p +区域5的中心下方。
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公开(公告)号：US5723890A
公开(公告)日：1998-03-03
申请号：US643760
申请日：1996-05-06
IPC分类号： H01L21/336 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/739 , H01L29/78 , H01L29/94
CPC分类号： H01L29/66712 , H01L29/0615 , H01L29/0619 , H01L29/0696 , H01L29/1095 , H01L29/7395 , H01L29/7802 , H01L29/0847 , H01L29/402 , H01L29/4238
摘要： A MOS type semiconductor device with improved voltage and avalanche withstand capability includes a rectangular channel region of the second conductivity type formed in a surface layer of a semiconductor substrate of the first conductivity type, a heavily doped well region formed in the central part of the channel region, source regions of the first conductivity type formed in a surface layer of the channel region, and a surface MOS structure. The quadrangular cells are arranged so that a side of the cell may contact with a side of the neighboring cell. By joining the short sides of the neighboring channel regions, protruding portions such as the corners, to which the avalanche current tend to localize, of the channel region are eliminated. As a result, the avalanche withstand capability of the MOSFET is improved. Further, since the curvature of the depletion layer becomes small, the withstand voltage is improved.
摘要翻译： 具有改善的电压和雪崩耐受能力的MOS型半导体器件包括形成在第一导电类型的半导体衬底的表面层中的第二导电类型的矩形沟道区，形成在沟道的中心部分的重掺杂阱区 形成在沟道区的表面层中的第一导电类型的区域，源极区和表面MOS结构。 四边形单元被布置成使得单元的一侧可以与相邻单元的一侧接触。 通过连接相邻通道区域的短边，消除了沟道区域中雪崩电流倾向于定位的拐角等突出部分。 结果，提高了MOSFET的雪崩承受能力。 此外，由于耗尽层的曲率变小，耐电压提高。
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公开(公告)号：US06246092B1
公开(公告)日：2001-06-12
申请号：US09042544
申请日：1998-03-17
IPC分类号： H03K1728
CPC分类号： H01L29/7808 , H01L27/0248 , H01L27/0629 , H01L29/402 , H01L29/7811 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： A MOS type semiconductor apparatus is provided that includes a first MOS type semiconductor device through which main current flows, and a second MOS type semiconductor device through which current that is smaller than the main current flows. The first and second MOS type semiconductor devices provided on the same semiconductor substrate have substantially the same structure, and have a common drain electrode. A gate electrode of the second MOS type semiconductor device is connected to the common drain electrode. The semiconductor apparatus further includes a plurality of pairs of Zener diodes which are connected in series and provided between the source electrode of the second MOS type semiconductor device and the gate electrode of the first MOS type semiconductor device. Each pair of Zener diodes are reversely connected to each other.
摘要翻译： 提供一种MOS型半导体装置，其包括主电流流过的第一MOS型半导体器件和小于主电流的电流流过的第二MOS型半导体器件。 设置在同一半导体衬底上的第一和第二MOS型半导体器件具有基本上相同的结构，并且具有公共漏电极。 第二MOS型半导体器件的栅电极连接到公共漏电极。 半导体装置还包括串联连接并设置在第二MOS型半导体器件的源电极和第一MOS型半导体器件的栅电极之间的多对齐纳二极管。 每对齐纳二极管彼此反向连接。
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公开(公告)号：US5869372A
公开(公告)日：1999-02-09
申请号：US555426
申请日：1995-11-09
申请人： Tatsuhiko Fujihira , Seiji Momota , Takeyoshi Nishimura , Kazutoshi Sugimura , Masao Yoshino , Takashi Kobayashi
发明人： Tatsuhiko Fujihira , Seiji Momota , Takeyoshi Nishimura , Kazutoshi Sugimura , Masao Yoshino , Takashi Kobayashi
IPC分类号： H01L21/28 , H01L21/265 , H01L21/266 , H01L21/306 , H01L21/316 , H01L21/336 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/823857 , H01L21/266
摘要： A semiconductor device manufacturing process is disclosed in which one processing step is reduced by replacing the photoresist film conventionally used for masking in the formation of the heavily doped n-type layer by an oxide film, and by monitoring, in the monitor region, the simultaneous formation of the contact holes in the oxide films different in the respective thickness thereof. An n+ region is formed by using a second insulation film and a polysilicon gate electrode formed on a semi-conductor wafer as masks for implanting arsenic ions. Further, a contact hole to be formed on a p-type region covered with a fourth insulation film and a second insulation film and a contact hole to be formed on the n+ region covered with the fourth insulation film are formed simultaneously under the monitoring of the formation of the contact holes in a monitor region.
摘要翻译： 公开了一种半导体器件制造方法，其中通过用氧化膜替代常规用于形成重掺杂n型层的掩模的光致抗蚀剂膜，并且通过在监测区域中监测同时 形成不同厚度的氧化膜中的接触孔。 通过使用形成在半导体晶片上的第二绝缘膜和多晶硅栅极作为用于注入砷离子的掩模来形成n +区。 此外，在被覆有第四绝缘膜的p型区域上形成的接触孔和被覆有第四绝缘膜的n +区域上形成的第二绝缘膜和接触孔同时形成在 在监视器区域中形成接触孔。
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公开(公告)号：US06548865B2
公开(公告)日：2003-04-15
申请号：US09799430
申请日：2001-03-05
IPC分类号： H01L2976
CPC分类号： H01L29/7808 , H01L27/0248 , H01L27/0629 , H01L29/402 , H01L29/7811 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： A MOS type semiconductor apparatus is provided that includes a first MOS type semiconductor device through which main current flows, and a second MOS type semiconductor device through which current that is smaller than the main current flows. The first and second MOS type semiconductor devices provided on the same semiconductor substrate have substantially the same structure, and have a common drain electrode. A gate electrode of the second MOS type semiconductor device is connected to the common drain electrode. The semiconductor apparatus further includes a plurality of pairs of Zener diodes which are connected in series and provided between the source electrode of the second MOS type semiconductor device and the gate electrode of the first MOS type semiconductor device. Each pair of Zener diodes are reversely connected to each other.
摘要翻译： 提供一种MOS型半导体装置，其包括主电流流过的第一MOS型半导体器件和小于主电流的电流流过的第二MOS型半导体器件。 设置在同一半导体衬底上的第一和第二MOS型半导体器件具有基本上相同的结构，并且具有公共漏电极。 第二MOS型半导体器件的栅电极连接到公共漏电极。 半导体装置还包括串联连接并设置在第二MOS型半导体器件的源电极和第一MOS型半导体器件的栅电极之间的多对齐纳二极管。 每对齐纳二极管彼此反向连接。
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公开(公告)号：US5912491A
公开(公告)日：1999-06-15
申请号：US746987
申请日：1996-11-19
IPC分类号： H01L21/336 , H01L29/06 , H01L29/10 , H01L29/739 , H01L29/78 , H01L29/76
CPC分类号： H01L29/1095 , H01L29/7802 , H01L29/0696
摘要： An n.sup.+ drain layer 2 and an n.sup.- layer 1 on n.sup.+ drain layer 2 constitute a substrate for the semiconductor arrangement. A p-type base region 3 is in the surface portion of n.sup.- layer 1. An n.sup.+ source region 6 is formed in the surface portion of p-type base region 3. A p.sup.+ region 5, deeper than n.sup.+ source region 6 and shallower than p-type base region 3, partially overlaps n.sup.+ source region 6 and extends thoroughly into the portion of p-type base region 3 surrounded by n.sup.+ source region 6. A channel portion 7 is in the surface portion of p-type base region 3 extending between n.sup.- layer 1 and n.sup.+ source regions 6. A gate electrode 8 is disposed above channel portion 7 with a gate insulation film 9 interposed therebetween. A source electrode 11 contacts with p.sup.+ region 5 and n.sup.+ source region 6. An inter-layer insulation film 10 on gate electrode 8 insulates source electrode 11 from gate electrode 8. A drain electrode 12 is on the surface of n.sup.+ drain layer 2. A junction face 20 of p-type base region 3 and n.sup.- layer 1 has a finite radius of curvature such that the depth from the surface of p.sup.+ region 5 to junction face 20 is deepest beneath the center of p.sup.+ region 5.
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公开(公告)号：US5757046A
公开(公告)日：1998-05-26
申请号：US691502
申请日：1996-08-02
IPC分类号： H01L29/06 , H01L29/08 , H01L29/10 , H01L29/739 , H01L29/78
CPC分类号： H01L29/0619 , H01L29/1095 , H01L29/7395 , H01L29/7802 , H01L29/0847
摘要： The invention improves the withstand voltage and avalanche withstand capability of a MOSFET, by preventing avalanche currents from localizing to the corners of the quadrangular cells of a MOSFET. The MOSFET includes a square channel region of the second conductivity type formed in a surface layer of a semiconductor substrate of the first conductivity type, a well region of high impurity concentration formed in the central portion of the channel region, a source region of the first conductivity type formed in a surface layer of the well region, and a MOS structure formed on the surface of the above described constituents. The cell structure, in which a diagonal of the square channel region and a diagonal of the nearest neighboring channel regions lie on a line, narrows a spacing between the corners of the neighboring channel regions to encourage pinch-off of a depletion layer and suppresses localization of avalanche currents to the corners of the channel regions. By connecting the corner of the neighboring channel regions with stripe regions of high resistivity, the depletion layer expands more easily.
摘要翻译： 本发明通过防止雪崩电流定位到MOSFET的四边形电池的角部来提高MOSFET的耐受电压和雪崩耐受能力。 MOSFET包括形成在第一导电类型的半导体衬底的表面层中的第二导电类型的正方形沟道区域，形成在沟道区域的中心部分中的高杂质浓度的阱区域，第一导电类型的源极区域 在阱区的表面层中形成的导电型，以及形成在上述成分的表面上的MOS结构。 其中平方通道区域的对角线和最近的相邻沟道区域的对角线位于一条线上的单元结构使相邻沟道区域的角部之间的间隔变窄，以促进耗尽层的夹断并抑制定位 的雪崩电流流向通道区域的拐角。 通过将相邻通道区域的角部连接成具有高电阻率的条带区域，耗尽层更容易扩展。
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