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    Memory module and an IC card
    1.
    发明授权
    Memory module and an IC card 失效
    内存模块和IC卡

    公开(公告)号：US5838549A

    公开(公告)日：1998-11-17

    申请号：US788423

    申请日：1997-01-27

    申请人： Tatsuya Nagata ,  Hiroya Shimizu ,  Atsushi Nakamura ,  Hideshi Fukumoto ,  Toshio Sugano

    发明人： Tatsuya Nagata ,  Hiroya Shimizu ,  Atsushi Nakamura ,  Hideshi Fukumoto ,  Toshio Sugano

    IPC分类号： H05K3/46 ,  H01L27/10 ,  H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H01R9/09

    CPC分类号： H05K1/117 ,  H01R12/721 ,  H05K1/0216 ,  H01R23/6873 ,  H05K1/0224 ,  H05K2201/0191 ,  H05K2201/09327 ,  H05K2201/09336 ,  H05K2201/09481 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2201/10159 ,  H05K2201/10689 ,  H05K3/429 ,  Y10S439/941

    摘要： In semiconductor modules having a plurality of semiconductor devices mounted on a multilayer printed circuit boards as the processing speed increases, a short circuit current flowing through CMOS devices in the semiconductor devices during operation can cause noise because of ground inductance or power supply inductance. This noise can result in erroneous operations. To solve this problem, the power supply layer or grand layer that is connected to either the power supply terminal Vcc or the ground terminal Gnd of each semiconductor memory, which is located farther from the connection terminals, is arranged closer to the semiconductor memories with this arrangement, the short circuit current flowing through the semiconductor memories is more strongly magnetically coupled with the power supply layer or ground layer arranged close to them. Thus, it is possible to reduce the effective inductance. This, in turn, reduces noise, making it possible to provide a semiconductor module with an increased processing speed.

    摘要翻译： 在处理速度增加时，具有安装在多层印刷电路板上的多个半导体器件的半导体模块中，在工作期间流过半导体器件中的CMOS器件的短路电流可能由于接地电感或电源电感而引起噪声。 这种噪音可能导致错误的操作。 为了解决这个问题，连接到距连接端子更远的每个半导体存储器的电源端子Vcc或接地端子Gnd的电源层或者大层被布置成更靠近半导体存储器 布置时，流过半导体存储器的短路电流与靠近它们布置的电源层或接地层更牢固地磁耦合。 因此，可以降低有效电感。 这反过来降低了噪声，使得可以提供具有增加的处理速度的半导体模块。

    Register without restriction of number of mounted memory devices and memory module having the same
    9.
    发明授权
    Register without restriction of number of mounted memory devices and memory module having the same 有权
    在不限制安装的存储器件的数量和具有相同的存储器模块的情况下进行注册

    公开(公告)号：US06707726B2

    公开(公告)日：2004-03-16

    申请号：US10206823

    申请日：2002-07-29

    申请人： Yoji Nishio ,  Seiji Funaba ,  Kayoko Shibata ,  Toshio Sugano ,  Hiroaki Ikeda ,  Takuo Iizuka ,  Masayuki Sorimachi

    发明人： Yoji Nishio ,  Seiji Funaba ,  Kayoko Shibata ,  Toshio Sugano ,  Hiroaki Ikeda ,  Takuo Iizuka ,  Masayuki Sorimachi

    IPC分类号： G11C700

    CPC分类号： G11C7/109 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/06 ,  G11C2207/107

    摘要： First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of ½ of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of signals which temporarily has two times. For example, one of the set of signals has only data contents of an odd-th command/address signal, and the other has only data contents of an even-th command/address signal. Since the set of signals has twice periods of the command/address signal, first and second post-processing flip-flop can latch signals in accordance with an internal clock signal generated by a delay locked loop circuit in a state in which a set-up time and a hold time are sufficiently assured.

    摘要翻译： 第一和第二预处理触发器通过具有外部时钟信号的1/2的频率的时钟及其反时钟来锁存输入到寄存器的命令/地址信号。 因此，命令/地址信号被分解成一组暂时具有两次的信号。 例如，该组信号之一仅具有奇数命令/地址信号的数据内容，而另一个仅具有偶数个命令/地址信号的数据内容。 由于该组信号具有两个命令/地址信号的周期，所以第一和第二后处理触发器可以根据由延迟锁定环电路产生的内部时钟信号来锁存信号， 时间和保持时间充分确保。