METHODS OF VERIFYING THAT A FIRST DEVICE AND A SECOND DEVICE ARE PHYSICALLY INTERCONNECTED

    公开(公告)号:US20200099541A1

    公开(公告)日:2020-03-26

    申请号:US16471973

    申请日:2017-02-10

    摘要: A method of verifying that a first device and a second device are physically interconnected is disclosed. The method is performed by a verifier and includes sending a challenge R1 to the first device, for use as basis for input to a first physical unclonable function, PUF,—part of the first device, receiving, a response, RES1, from the second device, the response RES1 being based on an output of a second PUF part of the second device, and verifying that the first device and the second device are interconnected for the case that the received response, RES1, and an expected response fulfills a matching criterion. A method in a first device and a method in a second device and corresponding devices, computer programs and computer program products are also disclosed.

    Generating Cryptographic Checksums
    5.
    发明申请

    公开(公告)号:US20180069706A1

    公开(公告)日:2018-03-08

    申请号:US15558844

    申请日:2015-05-04

    摘要: A method (400) of generating a cryptographic checksum for a message M(x) is provided. The method is performed by a communication device, such as a sender or a receiver, and comprises calculating (405) the cryptographic checksum as a first function g of a division of a second function of M(x), f(M(x)), modulo a generator polynomial p(x) of degree n, g(f(M(x)) mod p(x)). The generator polynomial is calculated (403) as p(x)=(1−x)·P1(x), and P/(x) is a primitive polynomial of degree n−1. The primitive polynomial is selected (402), based on a first cryptographic key, from the set of primitive polynomials of degree n−1 over a Galois Field. By replacing a standard checksum with a cryptographic checksum, an efficient message authentication is provided. The proposed cryptographic checksum may be used for providing integrity assurance on the message, i.e., for detecting random and intentional message changes, with a known level of security. The proposed checksum is capable of detecting double-bit errors which may be introduced by a Turbo code decoder.

    GENERATING CRYPTOGRAPHIC CHECKSUMS
    6.
    发明申请

    公开(公告)号:US20170244564A1

    公开(公告)日:2017-08-24

    申请号:US15504604

    申请日:2014-08-19

    IPC分类号: H04L9/32 H04L9/06

    摘要: A method (500) of generating a cryptographic checksum for a message M(x) is provided. The method comprises pseudo-randomly selecting (502) at least two irreducible polynomials pi(x). Each irreducible polynomial pi(x) is selected based on a first cryptographic key from the set of irreducible polynomials of degree ni over a Galois Field. The method further comprises calculating (503) a generator polynomial p(x) of degree n=formula (I) as a product of the N irreducible polynomials formula (II), and calculating (505) the cryptographic checksum as a first function g of a division of a second function of M(x), ƒ(M(x)), modulo p(x), i.e., g(ƒ(M(x)) mod p(x)). By replacing a standard checksum, such as a Cyclic Redundancy Check (CRC), with a cryptographic checksum, an efficient message authentication is provided. The proposed cryptographic checksum may be used for providing integrity assurance on the message, i.e., for detecting random and intentional message changes, with a known level of security. Further, a corresponding computer program, a corresponding computer program product, and a checksum generator for generating a cryptographic checksum, are provided. Σ i = 1 N  n i ( I ) p i  ( x ) , p  ( x ) = Π i = 1 N  p i  ( x ) , ( II )

    STREAM CIPHERING TECHNIQUE
    9.
    发明申请

    公开(公告)号:US20170338946A1

    公开(公告)日:2017-11-23

    申请号:US15535994

    申请日:2014-12-17

    IPC分类号: H04L9/06 H04L9/08

    摘要: A technique for generating a keystream (128) for ciphering or deciphering a data stream (122) is provided. As to a method aspect of the technique, a nonlinear feedback shift register, NLFSR (112), including n register stages implemented in a Galois configuration is operated. At least one register stage of the implemented n register stages is representable by at least one register stage of a linear feedback shift register, LFSR. A first subset of the implemented n register stages is representable by a second subset of a second NLFSR. A number of register stages receiving a nonlinear feedback in the second NLFSR is greater than one and less than a number of register stages receiving a nonlinear feedback in the implemented NLFSR. The keystream (128) is outputted from a nonlinear output function (118). An input of the nonlinear output function (118) is coupled to at least two of the implemented n register stages of the NLFSR (112).