公开(公告)号：US20080150610A1

公开(公告)日：2008-06-26

申请号：US11643492

申请日：2006-12-21

申请人： Terence Magee ,  Thomas Hughes ,  Cheng- Gang Kong

发明人： Terence Magee ,  Thomas Hughes ,  Cheng- Gang Kong

IPC分类号： H01L35/00

CPC分类号： G06F1/10 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C7/227 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

摘要： The present invention is directed to a method for compensating for process, voltage, and temperature variation without complex online/offline swapping of data paths requiring a dedicated FIFO (First-in First-out) buffer design. Delay cells are trained for each clock path (namely a Functional delay) and a spare delay cell is trained. A ratio is calculated for each Functional delay cell by dividing the Functional delay cells' setting into the spare delay cells' one-fourth cycle setting. These ratios reflect any process variation. Functional mode is then entered and a Master-Slave approach switched to, during which the spare delay cell repeats the training sequence continuously while the Functional delay cells delay the clocks from the RAM (Random Access Memory). Each Functional delay cell is updated at the end of each training sequence of the spare delay cell, compensating for voltage and temperature change, by dividing the ratio into the new spare delay cell one-fourth cycle setting.

摘要翻译： 本发明涉及一种用于补偿过程，电压和温度变化的方法，而不需要专用FIFO（先进先出）缓冲器设计的数据路径的复杂在线/离线交换。 对每个时钟路径（即功能延迟）训练延迟单元，并且对备用延迟单元进行训练。 通过将功能延迟单元的设置划分为备用延迟单元的四分之一周期设置，为每个功能延迟单元计算一个比率。 这些比率反映了任何过程变化。 然后进入功能模式，并切换主从方式，在此期间，备用延迟单元连续重复训练序列，而功能延迟单元延迟来自RAM（随机存取存储器）的时钟。 每个功能延迟单元在备用延迟单元的每个训练序列结束时被更新，通过将比率除以新的备用延迟单元四分之一周期设置来补偿电压和温度变化。

公开(公告)号：US07454303B2

公开(公告)日：2008-11-18

申请号：US11643492

申请日：2006-12-21

申请人： Terence Magee ,  Thomas Hughes ,  Cheng-Gang Kong

发明人： Terence Magee ,  Thomas Hughes ,  Cheng-Gang Kong

IPC分类号： G06F3/00

CPC分类号： G06F1/10 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C7/227 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

摘要： The present invention is directed to a method for compensating for process, voltage, and temperature variation without complex online/offline swapping of data paths requiring a dedicated FIFO(First-in First-out) buffer design. Delay cells are trained for each clock path (namely a Functional delay) and a spare delay cell is trained. A ratio is calculated for each Functional delay cell by dividing the Functional delay cells' setting into the spare delay cells' one-fourth cycle setting. These ratios reflect any process variation. Functional mode is then entered and a Master-Slave approach switched to, during which the spare delay cell repeats the training sequence continuously while the Functional delay cells delay the clocks from the RAM(Random Access Memory). Each Functional delay cell is updated at the end of each training sequence of the spare delay cell, compensating for voltage and temperature change, by dividing the ratio into the new spare delay cell one-fourth cycle setting.

摘要翻译： 本发明涉及一种用于补偿过程，电压和温度变化的方法，而不需要专用FIFO（先进先出）缓冲器设计的数据路径的复杂在线/离线交换。 对每个时钟路径（即功能延迟）训练延迟单元，并且对备用延迟单元进行训练。 通过将功能延迟单元的设置划分为备用延迟单元的四分之一周期设置，为每个功能延迟单元计算一个比率。 这些比率反映了任何过程变化。 然后进入功能模式，并切换主从方式，在此期间，备用延迟单元连续重复训练序列，而功能延迟单元延迟来自RAM（随机存取存储器）的时钟。 每个功能延迟单元在备用延迟单元的每个训练序列结束时被更新，通过将比率除以新的备用延迟单元四分之一周期设置来补偿电压和温度变化。

公开(公告)号：US07839716B2

公开(公告)日：2010-11-23

申请号：US12339232

申请日：2008-12-19

申请人： Cheng-Gang Kong ,  Thomas Hughes

发明人： Cheng-Gang Kong ,  Thomas Hughes

IPC分类号： G11C8/16

CPC分类号： G11C8/18 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C8/12

摘要： Apparatus and systems for improved PVT invariant fast rank switching in a DDR3 memory subsystem. A clock skew control circuit is provided between a memory controller and a DDR3 SDRAM memory subsystem to adjust skew between the DDR3 clock signal and data related signals (e.g., DQ and/or DQS). A initial write-leveling procedure determines the correct skew and programs a register file in the skew adjustment circuit. The register file includes a register for each of multiple ranks in the DDR3 memory. The values in each register serve to control selection of alignment of the data related signals to align with one of multiple phase shifted versions of a 1× DDR3 clock signal. The phase shifted clock signals are generated by clock divider circuits from a 2× DDR clock signal and use of a single fixed delay line approximating ⅛ of a 1× DDR3 clock period.

摘要翻译： 用于改进DDR3存储器子系统中的PVT不变快速级别切换的装置和系统。 时钟偏移控制电路设置在存储器控制器和DDR3 SDRAM存储器子系统之间，以调整DDR3时钟信号与数据相关信号（例如DQ和/或DQS）之间的偏差。 初始写入调平过程确定正确的偏移，并对偏斜调整电路中的寄存器文件进行编程。 寄存器文件包括DDR3存储器中多个级别中的每一个的寄存器。 每个寄存器中的值用于控制数据相关信号的对准选择，以与1×DDR3时钟信号的多个相移版本中的一个对准。 相移时钟信号由时钟分频器电路从2×DDR时钟信号产生，并使用近似1×DDR3时钟周期的单个固定延迟线。

公开(公告)号：US20080068911A1

公开(公告)日：2008-03-20

申请号：US11523139

申请日：2006-09-19

申请人： Thomas Hughes ,  Cheng-Gang Kong

发明人： Thomas Hughes ,  Cheng-Gang Kong

IPC分类号： G11C7/04

CPC分类号： G11C7/04 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2254

摘要： The present invention is a method for data path voltage and temperature compensation. The method includes configuring an offline data path to match an online data path. The method further includes compensating the offline data path for voltage and temperature variation. The method further includes swapping the offline data path with the online data path. Further, swapping occurs automatically without interruption of data flow along the data paths.

摘要翻译： 本发明是数据路径电压和温度补偿的方法。 该方法包括配置脱机数据路径以匹配在线数据路径。 该方法还包括补偿离线数据路径的电压和温度变化。 该方法还包括将离线数据路径与在线数据路径进行交换。 此外，交换自动发生而不中断沿数据路径的数据流。

公开(公告)号：US07969799B2

公开(公告)日：2011-06-28

申请号：US12109643

申请日：2008-04-25

申请人： Derrick Sai-Tang Butt ,  Cheng-Gang Kong ,  Terence J. Magee ,  Thomas Hughes

发明人： Derrick Sai-Tang Butt ,  Cheng-Gang Kong ,  Terence J. Magee ,  Thomas Hughes

IPC分类号： G11C7/10 ,  G11C7/00 ,  G11C8/00 ,  G11C8/18

CPC分类号： G11C7/1006

摘要： A memory interface physical layer macro including one or more embedded input/output (I/O) buffers, one or more memory interface hardmacros and control logic. The one or more embedded input/output (I/O) buffers support a plurality of I/O supply voltage levels. The one or more memory interface hardmacros are coupled to the one or more embedded I/O buffers. The control logic controls the one or more hardmacros and the one or more I/O buffers.

摘要翻译： 包括一个或多个嵌入式输入/输出（I / O）缓冲器，一个或多个存储器接口硬件和控制逻辑的存储器接口物理层宏。 一个或多个嵌入式输入/输出（I / O）缓冲器支持多个I / O电源电压电平。 一个或多个存储器接口hardmacros耦合到一个或多个嵌入式I / O缓冲器。 控制逻辑控制一个或多个硬件和一个或多个I / O缓冲器。

公开(公告)号：US20100157700A1

公开(公告)日：2010-06-24

申请号：US12339232

申请日：2008-12-19

申请人： Cheng-Gang Kong ,  Thomas Hughes

发明人： Cheng-Gang Kong ,  Thomas Hughes

IPC分类号： G11C8/18 ,  G11C7/00

CPC分类号： G11C8/18 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C8/12

摘要： Apparatus and systems for improved PVT invariant fast rank switching in a DDR3 memory subsystem. A clock skew control circuit is provided between a memory controller and a DDR3 SDRAM memory subsystem to adjust skew between the DDR3 clock signal and data related signals (e.g., DQ and/or DQS). A initial write-leveling procedure determines the correct skew and programs a register file in the skew adjustment circuit. The register file includes a register for each of multiple ranks in the DDR3 memory. The values in each register serve to control selection of alignment of the data related signals to align with one of multiple phase shifted versions of a 1× DDR3 clock signal. The phase shifted clock signals are generated by clock divider circuits from a 2× DDR clock signal and use of a single fixed delay line approximating ⅛ of a 1× DDR3 clock period.

摘要翻译： 用于改进DDR3存储器子系统中的PVT不变快速级别切换的装置和系统。 时钟偏移控制电路设置在存储器控制器和DDR3 SDRAM存储器子系统之间，以调整DDR3时钟信号与数据相关信号（例如DQ和/或DQS）之间的偏差。 初始写入调平过程确定正确的偏移，并对偏斜调整电路中的寄存器文件进行编程。 寄存器文件包括DDR3存储器中多个级别中的每一个的寄存器。 每个寄存器中的值用于控制数据相关信号的对准选择，以与1×DDR3时钟信号的多个相移版本中的一个对准。 相移时钟信号由时钟分频器电路从2×DDR时钟信号产生，并使用近似1×DDR3时钟周期的单个固定延迟线。

公开(公告)号：US07571396B2

公开(公告)日：2009-08-04

申请号：US11523139

申请日：2006-09-19

申请人： Thomas Hughes ,  Cheng-Gang Kong

发明人： Thomas Hughes ,  Cheng-Gang Kong

IPC分类号： G06F17/50

CPC分类号： G11C7/04 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2254

摘要： The present invention is a method for data path voltage and temperature compensation. The method includes configuring an offline data path to match an online data path. The method further includes compensating the offline data path for voltage and temperature variation. The method further includes swapping the offline data path with the online data path. Further, swapping occurs automatically without interruption of data flow along the data paths.

摘要翻译： 本发明是数据路径电压和温度补偿的方法。 该方法包括配置脱机数据路径以匹配在线数据路径。 该方法还包括补偿离线数据路径的电压和温度变化。 该方法还包括将离线数据路径与在线数据路径进行交换。 此外，交换自动发生而不中断沿数据路径的数据流。

公开(公告)号：US20090091987A1

公开(公告)日：2009-04-09

申请号：US12109643

申请日：2008-04-25

申请人： Derrick Sai-Tang Butt ,  Cheng-Gang Kong ,  Terence J. Magee ,  Thomas Hughes

发明人： Derrick Sai-Tang Butt ,  Cheng-Gang Kong ,  Terence J. Magee ,  Thomas Hughes

IPC分类号： G11C7/00

CPC分类号： G11C7/1006

摘要： A memory interface physical layer macro including one or more embedded input/output (I/O) buffers, one or more memory interface hardmacros and control logic. The one or more embedded input/output (I/O) buffers support a plurality of I/O supply voltage levels. The one or more memory interface hardmacros are coupled to the one or more embedded I/O buffers. The control logic controls the one or more hardmacros and the one or more I/O buffers.

摘要翻译： 包括一个或多个嵌入式输入/输出（I / O）缓冲器，一个或多个存储器接口硬件和控制逻辑的存储器接口物理层宏。 一个或多个嵌入式输入/输出（I / O）缓冲器支持多个I / O电源电压电平。 一个或多个存储器接口hardmacros耦合到一个或多个嵌入式I / O缓冲器。 控制逻辑控制一个或多个硬件和一个或多个I / O缓冲器。

公开(公告)号：US08811528B2

公开(公告)日：2014-08-19

申请号：US12954028

申请日：2010-11-24

申请人： Thomas Hughes ,  Victor K. Suen

发明人： Thomas Hughes ,  Victor K. Suen

IPC分类号： H04L25/49

CPC分类号： H04L25/03343

摘要： Transmitter-based techniques are provided for compensation of intersymbol interference and/or simultaneous switching outputs, using selective pulse width modulation. One or more signals are transmitted by detecting whether one or more of said signals satisfy one or more predefined signal corruption conditions, wherein said predefined signal corruption conditions indicate that one or more of said signals are anticipated to exhibit one or more of intersymbol interference and simultaneous switching outputs; and selecting a delay for one or more of the signals based on the one or more predefined signal corruptions conditions. The predefined signal corruption conditions comprise, for example, (i) digital data encoded in the one or more signals maintaining a same binary value for two or more consecutive clock cycles (to indicate intersymbol interference); and (ii) a predefined minimum number of aggressor data edges in digital data encoded in the one or more signals, and a corresponding predefined number of victim data edges in the digital data encoded in the one or more signals, wherein the victim edges are moving in an opposite direction to the aggressor data edges (to indicate simultaneous switching outputs).

摘要翻译： 基于发射机的技术被提供用于补偿符号间干扰和/或同时切换输出，使用选择性脉宽调制。 通过检测一个或多个所述信号是否满足一个或多个预定义的信号损坏状况来发送一个或多个信号，其中所述预定信号损坏状况指示所述信号中的一个或多个预期会呈现符号间干扰和同时发生的一个或多个 切换输出; 以及基于所述一个或多个预定义的信号损坏条件来选择一个或多个所述信号的延迟。 预定义的信号损坏条件包括例如（i）在一个或多个信号中编码的数字数据，对于两个或更多个连续的时钟周期（指示符号间干扰）保持相同的二进制值; 和（ii）在一个或多个信号中编码的数字数据中的预定的最小数量的侵略者数据边缘，以及在一个或多个信号中编码的数字数据中的对应的预定数量的受害者数据边缘，其中受害者边缘移动 在与侵略者数据边缘相反的方向（以指示同时切换输出）。

公开(公告)号：US20080115556A1

公开(公告)日：2008-05-22

申请号：US11696446

申请日：2007-04-04

申请人： Thomas Hughes

发明人： Thomas Hughes

IPC分类号： B25B7/12

CPC分类号： B25B7/12 ,  B25B7/14 ,  F16K7/063

摘要： A tool reduces a flow of liquid or gas through a conduit. The tool includes a crimping section having a first crimping member with a first blunt section extending partially along an edge thereof and a second crimping member having a second blunt section extending partially along an edge thereof. The first and second members are pivotally engaged with one another. A handle section is connected to the crimping section. The handle section includes a first handle member connected to the first crimping member and a second handle member connected to the second crimping member. A hinge pivotally connects the first handle member to the second handle member. When the first and second handle members are pivoted about the hinge, the first and second crimping members are caused to pivot in a direction opposite to the respective first and second handle members.

摘要翻译： 工具减少液体或气体通过导管的流动。 该工具包括具有第一压接部件的压接部分，第一压接部件具有部分地沿其边缘延伸的第一钝部部分和具有部分地沿着其边缘延伸的第二钝部部分的第二压接部件。 第一和第二构件彼此枢转地接合。 手柄部分连接到压接部分。 手柄部分包括连接到第一压接构件的第一手柄构件和连接到第二压接构件的第二手柄构件。 铰链将第一手柄构件枢转地连接到第二手柄构件。 当第一和第二手柄构件围绕铰链枢转时，使第一和第二压接构件沿与相应的第一和第二手柄构件相反的方向枢转。