公开(公告)号：US4807011A

公开(公告)日：1989-02-21

申请号：US24930

申请日：1987-03-10

申请人： Terumoto Nonaka ,  Tadahiko Hotta

发明人： Terumoto Nonaka ,  Tadahiko Hotta

IPC分类号： H01L21/8222 ,  H01L27/06 ,  H01L27/098 ,  H01L29/772 ,  H01L29/80 ,  H01L29/68 ,  H01L27/04

CPC分类号： H01L29/7722 ,  H01L27/098 ,  H01L29/80

摘要： A semiconductor integrated circuit comprising a plurality of vertical static induction transistors (SITs) of normally-off type formed in a common semiconductor substrate in such a manner that the lateral dimension of the channel region of the SITs employed to form a hardware circuit region such as a logic circuit is designed greater than of the SITs which are employed to form a peripheral circuit region. Thus, it is possible to provide a semiconductor integrated circuit which concurrently satisfies a plurality of differently functioning semiconductor circuit requirements to exhibit different electric characteristics as represented by a high-speed operation and a high breakdown voltage.

摘要翻译： 一种半导体集成电路，包括形成在公共半导体衬底中的多个垂直静态感应晶体管（SIT），其以常规半导体衬底的方式使得SIT的沟道区域的横向尺寸形成硬件电路区域 逻辑电路被设计为大于用于形成外围电路区域的SIT的逻辑电路。 因此，可以提供同时满足多个不同功能的半导体电路要求的半导体集成电路，以呈现由高速操作和高击穿电压表示的不同的电特性。

公开(公告)号：US4409725A

公开(公告)日：1983-10-18

申请号：US309428

申请日：1981-10-07

申请人： Tadahiko Hotta ,  Terumoto Nonaka

发明人： Tadahiko Hotta ,  Terumoto Nonaka

IPC分类号： H01L21/8238 ,  H01L21/8249 ,  H01L27/085 ,  H01L21/22 ,  H01L21/306 ,  H01L29/76

CPC分类号： H01L21/8249 ,  H01L21/8238 ,  H01L27/085

摘要： A method of making a semiconductor integrated circuit on a semiconductor substrate containing thereon an SIT and an IG(MOS) FET or an SIT and C-MOS FETs, comprises a series of steps of making these functional semiconductor devices many of which steps are rendered to be common to the SIT and the FET. The gate region of said IG(MOS) FET is formed as a semiconductor gate layer which typically is made of polycrystalline silicon, and an active semiconductor area of said IG(MOS) FET is formed by using this semiconductor gate layer as the mask therefor.

摘要翻译： 在其上包含SIT和IG（MOS）FET或SIT和C-MOS FET的半导体衬底上制造半导体集成电路的方法包括使这些功能半导体器件成为许多步骤的一系列步骤 对于SIT和FET是常见的。 所述IG（MOS）FET的栅极区域形成为通常由多晶硅制成的半导体栅极层，并且通过使用该半导体栅极层作为掩模来形成所述IG（MOS）FET的有源半导体区域。

公开(公告)号：US4216038A

公开(公告)日：1980-08-05

申请号：US913006

申请日：1978-06-05

申请人： Jun-ichi Nishizawa ,  Yasunori Mochida ,  Terumoto Nonaka ,  Tadahiko Hotta ,  Shin Yamashita

发明人： Jun-ichi Nishizawa ,  Yasunori Mochida ,  Terumoto Nonaka ,  Tadahiko Hotta ,  Shin Yamashita

IPC分类号： H01L29/80 ,  H01L21/033 ,  H01L29/739 ,  H01L21/22

CPC分类号： H01L29/739 ,  H01L21/033 ,  Y10S438/942

摘要： In a semiconductor device of the type arranged so that the minority carriers are injected into a lightly-doped n type semiconductor layer from a heavily-doped p type semiconductor layer provided in the n type layer, that portion of the p type layer excluding a certain portion is separated from the n type layer by a separator layer to cause the p type layer to contact the n type layer only at the certain portion, whereby the carrier injection is restricted to occur within a limited region of the n type layer contacting the certain portion of the p type layer. The separator and the p type layer are formed, by relying on a self-alignment technique using a double-mask layer, as diffused regions partially overlapping each other with a good relative alignment in the n type layer.

摘要翻译： 在配置为使得少数载流子从设置在n型层中的重掺杂p型半导体层注入到轻掺杂n型半导体层中的类型的半导体器件中，除了一定的p型层之外的该部分 部分通过分隔层与n型层分离，使得p型层仅在某一部分与n型层接触，由此载流子注入被限制在n型层的有限区域内， p型层的一部分。 通过依靠使用双掩模层的自对准技术，形成分隔层和p型层，作为在n型层中以良好的相对取向部分地彼此重叠的扩散区域。

公开(公告)号：US4377900A

公开(公告)日：1983-03-29

申请号：US257664

申请日：1981-04-27

申请人： Terumoto Nonaka ,  Tadahiko Hotta

发明人： Terumoto Nonaka ,  Tadahiko Hotta

IPC分类号： H01L21/335 ,  H01L29/739 ,  H01L29/772 ,  H01L29/80 ,  H01L21/223

CPC分类号： H01L29/66416 ,  H01L29/739 ,  H01L29/7722 ,  H01L29/80

摘要： A method of manufacturing an SIT or SITL device, comprising simultaneous formation of a gate doping aperture and contact apertures for a source and a drain. Firstly, a gate region is doped through the doping aperture with the contact apertures being covered by a mask. Then, a source region is doped so as to be in self-alignment relation relative to the gate region and a source contact portion is doped so as to be in self-alignment relation relative to the source region and the gate region, whereby the mask alignments are eliminated and packing density is enhanced.

摘要翻译： 一种制造SIT或SITL器件的方法，包括同时形成用于源极和漏极的栅极掺杂孔和接触孔。 首先，通过掺杂孔掺杂栅极区域，接触孔被掩模覆盖。 然后，源极区域被掺杂成相对于栅极区域处于自对准关系，并且源极接触部分被掺杂以相对于源极区域和栅极区域处于自对准关系，由此掩模 消除排列并提高包装密度。

公开(公告)号：US4205334A

公开(公告)日：1980-05-27

申请号：US925624

申请日：1978-07-17

申请人： Terumoto Nonaka ,  Tadahiko Hotta ,  Shin Yamashita

发明人： Terumoto Nonaka ,  Tadahiko Hotta ,  Shin Yamashita

IPC分类号： H01L29/80 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L27/02 ,  H01L27/06 ,  H01L27/098 ,  H01L29/73 ,  H01L29/808

CPC分类号： H01L27/0225 ,  H01L27/0623 ,  H01L27/098 ,  H01L29/8083

摘要： An integrated semiconductor device including at least one first vertical-type junction field effect transistor (vertical JFET) having a triode-like unsaturated voltage-current characteristic and at least one second vertical JFET having a bipolar-transistor-like saturated voltage-current characteristic, both being integrally formed in a semiconductor body. Both the first and second vertical JFET are much similar in general arrangement to each other, thus allowing simultaneous forming thereof by the same manufacturing process, without sacrificing the good characteristics of these two types of transistors.

摘要翻译： 一种集成半导体器件，包括具有三极管状不饱和电压 - 电流特性的至少一个第一垂直型结型场效应晶体管（垂直JFET）和具有双极晶体管类饱和电压 - 电流特性的至少一个第二垂直JFET， 两者都整体地形成在半导体本体中。 第一和第二垂直JFET两者在一般布置中彼此非常相似，因此允许通过相同制造工艺同时形成它们，而不牺牲这两种类型的晶体管的良好特性。

公开(公告)号：US4200879A

公开(公告)日：1980-04-29

申请号：US954917

申请日：1978-10-26

申请人： Terumoto Nonaka ,  Tadahiko Hotta ,  Shin Yamashita

发明人： Terumoto Nonaka ,  Tadahiko Hotta ,  Shin Yamashita

IPC分类号： H01L29/80 ,  H01L21/331 ,  H01L27/02 ,  H01L29/73 ,  H01L29/739 ,  H01L27/04

CPC分类号： H01L29/739 ,  H01L27/0225

摘要： In an integrated semiconductor device of the IIL type which includes a switching transistor and an injector transistor for supplying carriers to drive the switching transistor, the switching transistor is a static induction transistor which comprises: cylindrical current channels for providing current paths between a source and drains; a control gate surrounding the outer boundaries of the channels to form pn junctions therebetween and being injected with carriers from the injector transistor to control the current flow in the channels; and floating gates disposed inside the respective channels to form pn junctions therebetween. The floating gates are electrically floating and have a potential affected by the potential of the control gate to contribute to the channel conduction controlling action together with the control gate.

摘要翻译： 在包括开关晶体管和用于提供载流子以驱动开关晶体管的注入晶体管的IIL类型的集成半导体器件中，开关晶体管是静态感应晶体管，其包括：用于在源极和漏极之间提供电流路径的圆柱形电流通道 ; 围绕通道的外边界的控制栅极，以在其间形成pn结，并且从注射器晶体管注入载流子，以控制通道中的电流; 以及布置在相应通道内的浮栅，以在它们之间形成pn结。 浮动栅极是电浮动的并且具有受控制栅极的电位影响的电位，以与控制栅极一起有助于沟道导通控制动作。

公开(公告)号：US5418179A

公开(公告)日：1995-05-23

申请号：US291728

申请日：1994-08-16

申请人： Tadahiko Hotta

发明人： Tadahiko Hotta

IPC分类号： H01L21/768 ,  H01L21/70

CPC分类号： H01L21/76895 ,  H01L21/823871 ,  H01L21/823814 ,  H01L21/823878 ,  Y10S148/019 ,  Y10S148/147

摘要： An integrated circuit is fabricated on a semiconductor substrate and comprises an n channel type field effect transistor, a p channel type field effect transistor and an interconnection coupled between the drain regions of the two field effect transistors, and each of the gate electrodes and the interconnection is provided with a polycrystalline silicon and a refractory metal silicide deposited over the polycrystalline silicon, wherein side spacers are eliminated from the gate electrodes and the interconnection, because no short circuiting takes place between the gate electrodes and the source and drain regions by virtue of the deposition of the refractory metal silicide.

摘要翻译： 集成电路制造在半导体衬底上，并且包括n沟道型场效应晶体管，ap沟道型场效应晶体管和耦合在两个场效应晶体管的漏极区之间的互连，并且每个栅电极和互连是 设置有沉积在多晶硅上的多晶硅和难熔金属硅化物，其中从栅电极和互连中去除侧间隔物，因为通过沉积在栅电极和源极和漏极区之间不发生短路 的难熔金属硅化物。

公开(公告)号：US4619035A

公开(公告)日：1986-10-28

申请号：US747175

申请日：1985-06-21

申请人： Tadahiko Hotta ,  Shingo Sakakibara

发明人： Tadahiko Hotta ,  Shingo Sakakibara

IPC分类号： H01L21/285 ,  H01L21/8222 ,  H01L21/40

CPC分类号： H01L21/8222 ,  H01L21/28537 ,  Y10S148/019 ,  Y10S148/147

摘要： A method of manufacturing a semiconductor device manufactures a semiconductor device provided with plural kinds of Schottky barrier diodes having different forward voltages on one substrate. The method includes (a) a step of forming at least one Schottky barrier diode of a first kind, and (b) a step of forming at least one Schottky barrier diode of a second kind. The step (a) is performed by placing a first metal layer at a first surface part of a silicon substrate, and then by silicifying the first metal layer. The step (b) is performed by plating, at a second surface part of the silicon substrate which is different from the first surface part of the silicon substrate, a second metal layer which consists of a metal different from the metal consisting of the first metal layer and then by silicifying the second metal layer. Thus a semiconductor device provided with plural kinds of Schottky barrier diodes having different forward voltages on one substrate which is suitable for STL (Schottky Transistor Logic) etc. is obtained.

摘要翻译： 制造半导体器件的方法制造在一个衬底上设置有具有不同正向电压的多种肖特基势垒二极管的半导体器件。 该方法包括（a）形成至少一种肖特基势垒二极管的步骤，和（b）形成至少一种第二类肖特基势垒二极管的步骤。 步骤（a）通过将第一金属层放置在硅衬底的第一表面部分，然后通过硅化第一金属层来进行。 步骤（b）通过在与硅衬底的第一表面部分不同的硅衬底的第二表面部分处电镀来执行第二金属层，该第二金属层由不同于由第一金属 然后通过硅化第二金属层。 因此，获得了在适用于STL（肖特基晶体管逻辑）等的一个基板上设置有具有不同正向电压的多种肖特基势垒二极管的半导体器件。

公开(公告)号：US4710265A

公开(公告)日：1987-12-01

申请号：US938010

申请日：1986-12-04

申请人： Tadahiko Hotta

发明人： Tadahiko Hotta

IPC分类号： H01L27/08 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/22 ,  B44C1/22 ,  C03C15/00 ,  H01L21/38

CPC分类号： H01L29/0638 ,  H01L21/76218 ,  Y10S438/975

摘要： A complementary MOS type integrated circuit is produced by a method which comprises the steps of: disposing a first mask material layer on the surface of a semiconductor substrate, the first mask material layer having a first impurity introducing region corresponding to a desired well forming pattern; forming a well region by selectively doping an impurity into the surface of the substrate through the first impurity introducing region; forming a second mask material layer in such a manner as to cover both the first impurity introducing region and the first mask material layer; disposing first and second mask layers on the second mask material layer, the first and second mask layers respectively corresponding to a first active region pattern within the well region and a second active region pattern outside the well region, thereby defining a second impurity introducing region corresponding to a desired parasitic channel stopper pattern between the stack portion of the first and second mask material layers and the first mask layer; selectively ion-implanting an impurity into the surface of the well region through the second impurity introducing region; selectively removing the first and second mask material layers by selective etching using the first and second mask layers; and selectively thermally oxidizing the surface of the substrate using the remaining portions of the first and second mask material layers as a mask, thereby simultaneously forming a field oxide film and a parasitic channel stopper region containing the implanted impurity. According to this method, the parasitic channel stopper region is self-aligned with both the well region and the field oxide film.

摘要翻译： 通过一种方法制造互补MOS型集成电路，该方法包括以下步骤：在半导体衬底的表面上设置第一掩模材料层，所述第一掩模材料层具有对应于期望的阱形成图案的第一杂质引入区域; 通过所述第一杂质导入区选择性地将杂质掺杂到所述衬底的表面中来形成阱区; 以覆盖所述第一杂质导入区域和所述第一掩模材料层的方式形成第二掩模材料层; 将第一和第二掩模层设置在第二掩模材料层上，第一和第二掩模层分别对应于阱区域内的第一有源区域图案和阱区域外部的第二有源区域图案，从而限定对应于第二掩模层的第二杂质引入区域 涉及在第一和第二掩模材料层的堆叠部分和第一掩模层之间的期望的寄生沟道阻挡图案; 通过第二杂质引入区选择性地将杂质离子注入阱区的表面; 通过使用第一和第二掩模层的选择性蚀刻来选择性地去除第一和第二掩模材料层; 并且使用第一和第二掩模材料层的剩余部分作为掩模选择性地热氧化基板的表面，从而同时形成包含注入的杂质的场氧化物膜和寄生沟道阻挡区域。 根据该方法，寄生沟道阻挡区域与阱区域和场氧化膜两者自对准。

公开(公告)号：US4870033A

公开(公告)日：1989-09-26

申请号：US21187

申请日：1987-03-03

申请人： Tadahiko Hotta ,  Osamu Hanagasaki

发明人： Tadahiko Hotta ,  Osamu Hanagasaki

IPC分类号： H01L21/768 ,  H01L21/28

CPC分类号： H01L21/28

摘要： An electrode using Ti or Zr having a highly reactive property but insuring a good and stable electric contact with a silicon semiconductor device surrounded by an oxygen atom-containing insulating film is realized with simplified and reduced manufacturing steps at a reduced cost by first revealing a selective surface region of the silicon semiconductor through a window, and then laminating thereon including the selective surface region a first metal layer of Ti or Zr and then a second metal layer of Mo or W to cover and protect the first metal layer from oxidation, and then etching away the laminated layers leaving that portion corresponding to the selective surface region of the device, and thereafter heating the assembly to form a silicide of the first metal with silicon of the underlying semiconductor. The upper metal layer is covered with a protective insulating layer to avoid oxidation of the upper metal layer. The step of covering with the protective insulating layer should preferably be taken before the heat-treatment for the silicide formation.

摘要翻译： 使用具有高反应性但是确保与由含氧原子的绝缘膜包围的硅半导体器件良好且稳定的电接触的Ti或Zr的电极通过简化和减少的制造步骤以降低的成本实现，首先显示选择性 通过窗口将硅半导体的表面区域覆盖，然后在其上层叠包含选择性表面区域的第一金属层Ti或Zr，然后第二金属层Mo或W以覆盖和保护第一金属层免受氧化，然后 蚀刻离开与该器件的选择性表面区域对应的部分的层叠层，然后加热该组件以形成第一金属的硅化物，其下面的半导体的硅。 上部金属层被保护绝缘层覆盖以避免上部金属层的氧化。 在保护绝缘层覆盖的步骤应优先在硅化物形成的热处理之前进行。