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公开(公告)号：US20080222360A1
公开(公告)日：2008-09-11
申请号：US12034454
申请日：2008-02-20
IPC分类号： G06F12/00
CPC分类号： G06F12/0853 , G06F9/3802 , G06F9/3808 , G06F9/3814 , G06F12/0846 , G06F12/0886
摘要： A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.
摘要翻译： 提供在并行处理器和主存储器之间并存储有存储在主存储器中的指令和数据的一部分的多端口指令/数据集成高速缓存具有多个存储体，并且多个端口包括指令端口单元 由用于访问来自并行处理器的指令的至少一个指令端口和由用于从并行处理器访问数据的至少一个数据端口组成的数据端口单元组成。 此外，可以从指令端口指定给存储体的数据宽度被设置为大于可以从数据端口指定给存储体的数据宽度。
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公开(公告)号：US07117291B2
公开(公告)日：2006-10-03
申请号：US10787240
申请日：2004-02-27
申请人： Hans Jurgen Mattausch , Tetsushi Koide , Tetsuo Hironaka , Hiroshi Uchida , Koh Johguchi , Zhaomin Zhu
发明人： Hans Jurgen Mattausch , Tetsushi Koide , Tetsuo Hironaka , Hiroshi Uchida , Koh Johguchi , Zhaomin Zhu
CPC分类号： G11C8/12
摘要： In a synchronous multi-port bank memory, registers/buffers receive a read/write signal and an address signal from each of external ports, receive and send a data signal to and from each of the external ports, and receive and send a port block signal. An access conflict management circuit receives the address signals from the registers and buffers and generates the port block signal when an access conflict to the bank occurs. A switching network receives the read/write signal and the address signal from the registers/buffers and generates a bank selection signal when no port block signal is received, so as to activate the selected bank. Thus, memory access cycle time is shortened. A synchronous 1-port bank memory is also constructed similarly.
摘要翻译： 在同步多端口组存储器中，寄存器/缓冲器从每个外部端口接收读/写信号和地址信号，从每个外部端口接收和发送数据信号，并接收和发送端口块 信号。 访问冲突管理电路从寄存器和缓冲器接收地址信号，并且当发生对存储体的访问冲突时产生端口块信号。 开关网络从寄存器/缓冲器接收读/写信号和地址信号，并且当没有接收到端口阻塞信号时产生存储体选择信号，以激活所选择的存储体。 因此，存储器访问周期时间缩短。 类似地构造同步1端口组存储器。
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公开(公告)号：US07694077B2
公开(公告)日：2010-04-06
申请号：US12034454
申请日：2008-02-20
IPC分类号： G06F12/00
CPC分类号： G06F12/0853 , G06F9/3802 , G06F9/3808 , G06F9/3814 , G06F12/0846 , G06F12/0886
摘要： A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.
摘要翻译： 提供在并行处理器和主存储器之间并存储有存储在主存储器中的指令和数据的一部分的多端口指令/数据集成高速缓存具有多个存储体，并且多个端口包括指令端口单元 由用于访问来自并行处理器的指令的至少一个指令端口和由用于从并行处理器访问数据的至少一个数据端口组成的数据端口单元组成。 此外，可以从指令端口指定给存储体的数据宽度被设置为大于可以从数据端口指定给存储体的数据宽度。
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公开(公告)号：US07360024B2
公开(公告)日：2008-04-15
申请号：US10687460
申请日：2003-10-15
IPC分类号： G06F12/00
CPC分类号： G06F12/0853 , G06F9/3802 , G06F9/3808 , G06F9/3814 , G06F12/0846 , G06F12/0886
摘要： A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.
摘要翻译： 提供在并行处理器和主存储器之间并存储有存储在主存储器中的指令和数据的一部分的多端口指令/数据集成高速缓存具有多个存储体，并且多个端口包括指令端口单元 由用于访问来自并行处理器的指令的至少一个指令端口和由用于从并行处理器访问数据的至少一个数据端口组成的数据端口单元组成。 此外，可以从指令端口指定给存储体的数据宽度被设置为大于可以从数据端口指定给存储体的数据宽度。
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公开(公告)号：US20050125594A1
公开(公告)日：2005-06-09
申请号：US10787240
申请日：2004-02-27
申请人： Hans Mattausch , Tetsushi Koide , Tetsuo Hironaka , Hiroshi Uchida , Koh Johguchi , Zhaomin Zhu
发明人： Hans Mattausch , Tetsushi Koide , Tetsuo Hironaka , Hiroshi Uchida , Koh Johguchi , Zhaomin Zhu
CPC分类号： G11C8/12
摘要： In a synchronous multi-port bank memory, registers/buffers receive a read/write signal and an address signal from each of external ports, receive and send a data signal to and from each of the external ports, and receive and send a port block signal. An access conflict management circuit receives the address signals from the registers and buffers and generates the port block signal when an access conflict to the bank occurs. A switching network receives the read/write signal and the address signal from the registers/buffers and generates a bank selection signal when no port block signal is received, so as to activate the selected bank. Thus, memory access cycle time is shortened. A synchronous 1-port bank memory is also constructed similarly.
摘要翻译： 在同步多端口组存储器中，寄存器/缓冲器从每个外部端口接收读/写信号和地址信号，从每个外部端口接收和发送数据信号，并接收和发送端口块 信号。 访问冲突管理电路从寄存器和缓冲器接收地址信号，并且当发生对存储体的访问冲突时产生端口块信号。 开关网络从寄存器/缓冲器接收读/写信号和地址信号，并且当没有接收到端口阻塞信号时产生存储体选择信号，以激活所选择的存储体。 因此，存储器访问周期时间缩短。 类似地构造同步1端口组存储器。
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6.发明授权公开(公告)号：US09977733B2
公开(公告)日：2018-05-22
申请号：US14378157
申请日：2012-03-30
申请人： Ken Takeuchi , Kousuke Miyaji , Koh Johguchi , Hiroki Fujii
发明人： Ken Takeuchi , Kousuke Miyaji , Koh Johguchi , Hiroki Fujii
CPC分类号： G06F12/0246 , G06F12/0238 , G06F12/0638 , G06F2212/7201 , G11C11/005 , G11C13/0002 , G11C13/0035
摘要： When a data utilization ratio R which is a utilization ratio of sectors in one page is not lower than a threshold value Rth1 and when write data is not frequently-rewritten data, a flash memory is controlled such that the write data is stored into the flash memory. When the data utilization ratio R which is the utilization ratio of sectors in one page is lower than the threshold value Rth1 or when the write data is frequently-rewritten data although the data utilization ratio R is not lower than the threshold value Rth1, a ReRAM is controlled such that the write data is stored into the ReRAM. This suppresses deterioration of the flash memory.
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公开(公告)号：US20150006796A1
公开(公告)日：2015-01-01
申请号：US14378157
申请日：2012-03-30
申请人： Ken Takeuchi , Kousuke Miyaji , Koh Johguchi , Hiroki Fujii
发明人： Ken Takeuchi , Kousuke Miyaji , Koh Johguchi , Hiroki Fujii
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0238 , G06F12/0638 , G06F2212/7201 , G11C11/005 , G11C13/0002 , G11C13/0035
摘要： When a data utilization ratio R which is a utilization ratio of sectors in one page is not lower than a threshold value Rth1 and when write data is not frequently-rewritten data, a flash memory is controlled such that the write data is stored into the flash memory. When the data utilization ratio R which is the utilization ratio of sectors in one page is lower than the threshold value Rth1 or when the write data is frequently-rewritten data although the data utilization ratio R is not lower than the threshold value Rth1, a ReRAM is controlled such that the write data is stored into the ReRAM. This suppresses deterioration of the flash memory.
摘要翻译： 当作为一页中的扇区的利用率的数据利用率R不低于阈值Rth1时，并且当写入数据不被频繁重写的数据时，控制闪速存储器，使得写入数据被存储到闪存中 记忆。 当一页中的扇区的利用率的数据利用率R低于阈值Rth1时，或者即使数据利用率R不低于阈值Rth1，即使写入数据被频繁重写， 被控制使得写入数据被存储到ReRAM中。 这样可以抑制闪存的劣化。
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