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    Method of making multi-level wiring in a semiconductor device
    2.
    发明授权
    Method of making multi-level wiring in a semiconductor device 有权
    在半导体器件中制造多层布线的方法

    公开(公告)号：US06579785B2

    公开(公告)日：2003-06-17

    申请号：US09767724

    申请日：2001-01-24

    申请人： Hiroshi Toyoda ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Hideaki Hirabayashi

    发明人： Hiroshi Toyoda ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Hideaki Hirabayashi

    IPC分类号： H01L2144

    CPC分类号： H01L21/76849 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of manufacturing a semiconductor device, which comprises the steps of forming an intermediate layer on an insulating layer, forming a groove in the intermediate layer and the insulating layer, forming a first barrier layer on the intermediate layer, depositing a wiring layer on the first barrier layer to thereby fill the groove with the wiring layer, performing a flattening treatment of the wiring layer, removing a surface portion of the wiring to thereby permit the surface of the wiring to be recessed lower than a surface of the insulating layer, thus forming a recessed portion, forming a second barrier layer on the intermediate layer and on an inner wall of the recessed portion, performing a flattening treatment of the second barrier layer, thereby, and selectively removing the intermediate layer, exposing the insulating layer.

    摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在绝缘层上形成中间层，在中间层中形成沟槽和绝缘层，在中间层上形成第一阻挡层，在其上沉积布线层 第一阻挡层，从而使布线层填充沟槽，对布线层进行平坦化处理，去除布线的表面部分，从而允许布线的表面比绝缘层的表面凹陷，因此 形成凹部，在所述中间层和所述凹部的内壁上形成第二阻挡层，对所述第二阻挡层进行平坦化处理，从而选择性地除去所述中间层，使所述绝缘层露出。

    Method of forming diffusion barrier for copper interconnects
    4.
    发明授权
    Method of forming diffusion barrier for copper interconnects 有权
    形成铜互连的扩散阻挡层的方法

    公开(公告)号：US06342444B1

    公开(公告)日：2002-01-29

    申请号：US09522595

    申请日：2000-03-10

    申请人： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Hiroshi Toyoda ,  Akihiro Kajita ,  Tetsuo Matsuda ,  Hisashi Kaneko

    发明人： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Hiroshi Toyoda ,  Akihiro Kajita ,  Tetsuo Matsuda ,  Hisashi Kaneko

    IPC分类号： H01L214763

    CPC分类号： H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A TiN film is selectively formed as a barrier layer on a Cu metal layer by selective removal of a Ti metal layer on the Si metal layer after the following steps of selectively forming a Si metal layer as an etching mask on an insulation film, forming a trench pattern by selective removal of the insulation film using the Si metal layer, forming a Cu metal layer in the trench pattern with the Si metal layer remained, forming the Ti metal layer on the Si metal layer and the Cu metal layer as a barrier material with a different kind of eutectic reaction with Cu from the reaction with the etching mask by heat-treatment in an atmosphere of nitrogen, and selectively nitriding the Ti metal layer on the Cu metal layer by heat-treatment of the Ti metal layer in an atmosphere of nitrogen.

    摘要翻译： 通过在绝缘膜上选择性地形成Si金属层作为蚀刻掩模的以下步骤之后，通过选择性地除去Si金属层上的Ti金属层，在Cu金属层上选择性地形成TiN膜作为阻挡层，形成 沟槽图案，通过使用Si金属层选择性去除绝缘膜，在沟槽图案中形成具有Si金属层的Cu金属层，在Si金属层上形成Ti金属层，将Cu金属层形成为阻挡材料 在氮气气氛中通过热处理与与蚀刻掩模的反应与Cu的不同种类的共晶反应，并且通过在气氛中热处理Ti金属层来选择性地氮化Cu金属层上的Ti金属层 的氮气。

    Electronic device manufacturing method
    5.
    发明授权
    Electronic device manufacturing method 失效
    电子元件制造方法

    公开(公告)号：US06764585B2

    公开(公告)日：2004-07-20

    申请号：US09985051

    申请日：2001-11-01

    申请人： Tetsuo Matsuda ,  Hiroshi Toyoda ,  Hisashi Kaneko

    发明人： Tetsuo Matsuda ,  Hiroshi Toyoda ,  Hisashi Kaneko

    IPC分类号： B05D512

    CPC分类号： H01L21/76874 ,  C23C18/165 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/405 ,  C23C18/54 ,  C23C28/00 ,  C25D7/123 ,  H01L21/2855 ,  H01L21/288 ,  H01L21/76867 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An electronic device manufacturing method comprises forming an insulating film above a substrate, forming a to-be-filled region which includes at least one of an interconnection groove and a hole in the insulating film, forming a first conductive film containing a catalyst metal which accelerates electroless plating, so as to line an internal surface of the to-be-filled region, forming a second conductive film on the first conductive film by the electroless plating, so as to line the internal surface of the to-be-filled region via the first conductive film, and forming a third conductive film on the second conductive film by electroplating, so as to fill the to-be-filled region via the first conductive film and the second conductive film.

    摘要翻译： 一种电子器件制造方法，包括在基板上形成绝缘膜，形成包含所述绝缘膜中的互连槽和孔中的至少一个的待填充区域，形成含有催化剂金属的第一导电膜，其加速 化学镀，以便将要填充区域的内表面排列，通过化学镀在第一导电膜上形成第二导电膜，以便将被填充区域的内表面经由 第一导电膜，并且通过电镀在第二导电膜上形成第三导电膜，以便经由第一导电膜和第二导电膜填充待填充区域。

    Plating method
    7.
    发明授权
    Plating method 失效
    电镀方法

    公开(公告)号：US07575664B2

    公开(公告)日：2009-08-18

    申请号：US11135328

    申请日：2005-05-24

    申请人： Tetsuo Matsuda ,  Hisashi Kaneko ,  Katsuya Okumura

    发明人： Tetsuo Matsuda ,  Hisashi Kaneko ,  Katsuya Okumura

    IPC分类号： C25D21/12

    CPC分类号： C25D5/16 ,  C25D5/02 ,  C25D5/06 ,  C25D7/123 ,  C25D17/001 ,  C25D17/12 ,  H01L21/2885 ,  H01L21/76877 ,  H05K3/423

    摘要： A cathode potential is applied to a conductive layer formed on a substrate having a depression pattern. A plating solution in electrical contact with an anode is supplied to the conductive layer to form a plating film on the conductive layer. At this time, the plating solution is supplied by causing an impregnated member containing the plating solution to face the conductive layer. Since the plating solution stays in the depression, a larger amount of plating solution is supplied than on the upper surface of the substrate, and the plating rate of the plating film in the depression increases. Consequently, the plating film can be preferentially formed in the depression such as a groove or hole.

    摘要翻译： 对形成在具有凹陷图案的基板上的导电层施加阴极电位。 将与阳极电接触的电镀溶液供给到导电层，以在导电层上形成镀膜。 此时，通过使包含电镀液的浸渍部件面对导电层而供给电镀液。 由于电镀溶液滞留在凹陷中，所以与基板的上表面相比，供给电镀液的量较多，因此抑制了镀膜的镀覆速度。 因此，可以在诸如凹槽或孔的凹陷中优先地形成镀膜。

    Method of manufacturing a semiconductor device
    10.
    发明授权
    Method of manufacturing a semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US06518177B1

    公开(公告)日：2003-02-11

    申请号：US09783561

    申请日：2001-02-15

    申请人： Takashi Kawanoue ,  Junichi Wada ,  Tetsuo Matsuda ,  Hisashi Kaneko

    发明人： Takashi Kawanoue ,  Junichi Wada ,  Tetsuo Matsuda ,  Hisashi Kaneko

    IPC分类号： H01L214763

    CPC分类号： H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/53209 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device is formed by a compound film &agr;&ggr;x made of at least one element &agr; selected from metal elements and at least one element &ggr; selected from the group consisting of boron, carbon, and nitrogen on a base layer containing oxygen (O), and forming a compound film &agr;&ggr;yOz by causing the compound film &agr;&ggr;x to reduce the base layer and thereby oxidizing the compound film &agr;&ggr;x on an interface of the compound film &agr;&ggr;x and the base layer, wherein each of x and y is a ratio of the number of atoms of the element &ggr; to the number of atoms of the element &agr;, and z is a ratio of the number of atoms of the oxygen to the number of atoms of the element &agr;.

    摘要翻译： 通过由选自金属元素的至少一种元素α和在含氧（O）的基底层上选自硼，碳和氮的至少一种元素γ制成的化合物膜，形成半导体器件，以及 通过使化合物膜alphagammax减少基底层从而氧化化合物膜的碱性和底层的界面上的化合物膜，形成化合物膜alphagammayOz，其中x和y分别为原子数 元素γ与元素α的原子数之比，z是氧原子数与元素α原子数之比。