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    IMAGE SEGMENTATION APPARATUS, IMAGE SEGMENTATION METHOD, AND IMAGE SEGMENTATION INTERGRATED CIRCUIT
    1.
    发明申请
    IMAGE SEGMENTATION APPARATUS, IMAGE SEGMENTATION METHOD, AND IMAGE SEGMENTATION INTERGRATED CIRCUIT 有权
    图像分割装置，图像分割方法和图像分割集成电路

    公开(公告)号：US20080187223A1

    公开(公告)日：2008-08-07

    申请号：US12098650

    申请日：2008-04-07

    申请人： Tetsushi KOIDE ,  Hans Jurgen Mattausch ,  Takashi Morimoto ,  Youmei Harada

    发明人： Tetsushi KOIDE ,  Hans Jurgen Mattausch ,  Takashi Morimoto ,  Youmei Harada

    IPC分类号： G06K9/34

    CPC分类号： G06K9/342 ,  G06K9/00986 ,  G06T7/11 ,  G06T7/20 ,  G06T2200/28 ,  G06T2207/10016

    摘要： In a boundary active only scheme proposed by the present invention, only a cell in a boundary of region growth is brought into an active mode, and the other cells are brought into a standby mode. The respective cells perform state transition in parallel, and decision of the state transition performed for each clock cycle is not performed in a case where any of the three conditions that none of the adjacent cells is ignited, the cell itself is already ignited, and the cell already belongs to a certain divided region is satisfied. Therefore the number of simultaneously operating cells and that of coupling weight registers are minimized, and control is automatically executed to reduce power consumption.

    摘要翻译： 在本发明提出的仅边界有效方案中，只有区域增长边界中的单元才能进入活动模式，其他单元进入待机模式。 各个小区并行执行状态转换，并且在没有相邻小区被点燃的三个条件，小区本身已被点燃的情况下，不执行对于每个时钟周期执行的状态转换的判定，并且 细胞已经属于某个分割区域。 因此，同时工作的单元和耦合重量寄存器的数量最小化，自动执行控制以降低功耗。

    ASSOCIATIVE MEMORY
    2.
    发明申请
    ASSOCIATIVE MEMORY 有权
    相关记忆

    公开(公告)号：US20130114322A1

    公开(公告)日：2013-05-09

    申请号：US13466381

    申请日：2012-05-08

    申请人： Hans Juergen MATTAUSCH ,  Tetsushi KOIDE ,  Masahiro YASUDA ,  Seiryu SASAKI

    发明人： Hans Juergen MATTAUSCH ,  Tetsushi KOIDE ,  Masahiro YASUDA ,  Seiryu SASAKI

    IPC分类号： G11C15/00

    CPC分类号： G11C15/04

    摘要： An associative memory that can reduce search errors is provided. An associative memory includes R distance/time conversion circuits DT1 to DTR. The R distance/time conversion circuits DT1 to DTR each include a NAND circuit 40 and N bit stages 41 to 4k. The N bit stages 41 to 4k delay a signal from the NAND circuit 40 by longer delay time as the distance between reference data and search data is greater and oscillate the signal. Among R oscillation signals output from the distance/time conversion circuits DT1 to DTR, the earliest changing oscillation signal is detected as an oscillation signal for the Winner row.

    摘要翻译： 提供了可以减少搜索错误的关联内存。 关联存储器包括R个距离/时间转换电路DT1至DTR。 R距离/时间转换电路DT1至DTR各自包括NAND电路40和N位级41至4k。 随着参考数据和搜索数据之间的距离更大并使信号振荡，N位级41至4k将来自NAND电路40的信号延迟更长的延迟时间。 在从距离/时间转换电路DT1至DTR输出的R振荡信号中，将最早改变的振荡信号作为Winner行的振荡信号进行检测。