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1.发明授权Associative memory apparatus for searching data in which manhattan distance is minimum 有权用于搜索曼哈顿距离最小的数据的关联存储装置公开(公告)号：US07113416B2
公开(公告)日：2006-09-26
申请号：US10915430
申请日：2004-08-11
申请人： Tetsushi Koide , Hans Jurgen Mattausch , Yuji Yano
发明人： Tetsushi Koide , Hans Jurgen Mattausch , Yuji Yano
IPC分类号： G11C7/00
CPC分类号： G11C15/00
摘要： In the present invention, focusing on the point that the number of transistors can be reduced to about ⅖ of that in a prior art due to an absolute-value-of-difference calculating circuit for an associative memory being configured of an addition circuit and a bit inversion circuit. The absolute-value-of-difference calculating circuit is built in a fully-parallel type associative memory as a unit comparison circuit, and all of the outputs of the absolute-value-of-difference calculating circuits for which the number of comparisons thereof are prepared are input to weight comparison circuits, whereby the calculation of the Manhattan distance between the search data and the reference data is carried out. In accordance with the configuration, because a Manhattan distance calculating circuit can be realized by a fewer number of transistors and with a small area, an associative memory apparatus as well can be realized at a low power consumption and with a small area.
摘要翻译： 在本发明中，由于由联结存储器的差值绝对值计算电路由加法电路构成，因此重点在于现有技术中晶体管的数目可以减少到约2/5， 和位反转电路。 差分绝对值计算电路作为单位比较电路而构成全平行型联想存储器，并且其比较数的差分计算电路的绝对值计算电路的所有输出 准备的输入到加权比较电路，由此执行搜索数据和参考数据之间的曼哈顿距离的计算。 根据该结构，由于可以通过较少数量的晶体管和小面积来实现曼哈顿距离计算电路，所以可以在低功耗和小面积上实现关联存储装置。
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2.发明授权公开(公告)号：US07561743B2
公开(公告)日：2009-07-14
申请号：US11015038
申请日：2004-12-20
CPC分类号： G06K9/66 , G06K9/00986 , Y10S707/99937
摘要： In an associative memory, when a reference data having the minimum distance with respect to an input data is detected as winner, it is determined whether or not a distance between the input data and winner is less than a threshold value. If the distance is less than the threshold value, it is determined that the reference data detected as winner matches with the input data, and then, a rank of the reference data is improved. If the distance is more than the threshold value, it is determined that the reference data is data different from the input data, and then, the input data is written as new reference data to the associative memory and replaces the reference data with the lowest rank. The upper positions of rank form as a long-term memory, and the lower positions thereof form as a short-term memory.
摘要翻译： 在关联存储器中，当检测到具有相对于输入数据的最小距离的参考数据作为胜者时，确定输入数据和赢者之间的距离是否小于阈值。 如果该距离小于阈值，则判断为被检测为胜者的参考数据与输入数据匹配，然后提高参考数据的等级。 如果距离大于阈值，则确定参考数据是与输入数据不同的数据，然后将输入数据作为新的参考数据写入关联存储器，并将最低等级的参考数据替换 。 作为长期记忆的排名形式的上位，其较低的位置形成为短期记忆。
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3.发明授权公开(公告)号：US07526127B2
公开(公告)日：2009-04-28
申请号：US10915559
申请日：2004-08-11
IPC分类号： G06K9/34
CPC分类号： G06K9/342 , G06K9/00986 , G06T7/11 , G06T7/20 , G06T2200/28 , G06T2207/10016
摘要： In a boundary active only scheme proposed by the present invention, only a cell in a boundary of region growth is brought into an active mode, and the other cells are brought into a standby mode. The respective cells perform state transition in parallel, and decision of the state transition performed for each clock cycle is not performed in a case where any of the three conditions that none of the adjacent cells is ignited, the cell itself is already ignited, and the cell already belongs to a certain divided region is satisfied. Therefore the number of simultaneously operating cells and that of coupling weight registers are minimized, and control is automatically executed to reduce power consumption.
摘要翻译： 在本发明提出的仅边界有效方案中，只有区域增长边界中的单元才能进入活动模式，其他单元进入待机模式。 各个小区并行执行状态转换，并且在没有相邻小区被点燃的三个条件，小区本身已被点燃的情况下，不执行对于每个时钟周期执行的状态转换的判定，并且 细胞已经属于某个分割区域。 因此，同时工作的单元和耦合重量寄存器的数量最小化，自动执行控制以降低功耗。
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公开(公告)号：US07117291B2
公开(公告)日：2006-10-03
申请号：US10787240
申请日：2004-02-27
申请人： Hans Jurgen Mattausch , Tetsushi Koide , Tetsuo Hironaka , Hiroshi Uchida , Koh Johguchi , Zhaomin Zhu
发明人： Hans Jurgen Mattausch , Tetsushi Koide , Tetsuo Hironaka , Hiroshi Uchida , Koh Johguchi , Zhaomin Zhu
CPC分类号： G11C8/12
摘要： In a synchronous multi-port bank memory, registers/buffers receive a read/write signal and an address signal from each of external ports, receive and send a data signal to and from each of the external ports, and receive and send a port block signal. An access conflict management circuit receives the address signals from the registers and buffers and generates the port block signal when an access conflict to the bank occurs. A switching network receives the read/write signal and the address signal from the registers/buffers and generates a bank selection signal when no port block signal is received, so as to activate the selected bank. Thus, memory access cycle time is shortened. A synchronous 1-port bank memory is also constructed similarly.
摘要翻译： 在同步多端口组存储器中，寄存器/缓冲器从每个外部端口接收读/写信号和地址信号，从每个外部端口接收和发送数据信号，并接收和发送端口块 信号。 访问冲突管理电路从寄存器和缓冲器接收地址信号，并且当发生对存储体的访问冲突时产生端口块信号。 开关网络从寄存器/缓冲器接收读/写信号和地址信号，并且当没有接收到端口阻塞信号时产生存储体选择信号，以激活所选择的存储体。 因此，存储器访问周期时间缩短。 类似地构造同步1端口组存储器。
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5.发明授权公开(公告)号：US07881525B2
公开(公告)日：2011-02-01
申请号：US11508901
申请日：2006-08-24
IPC分类号： G06K9/00
CPC分类号： G06K9/00986 , G06K9/6272
摘要： The present invention is directed to a pattern recognition system in which new reference data to be added is efficiently learned. In the pattern recognition system, there is performed the calculation of distances equivalent to similarities between input data of a pattern search target and a plurality of reference data, and based on input data of a fixed number of times corresponding to the reference data set as a recognized winner, a gravity center thereof is calculated to optimize the reference data. Furthermore, a threshold value is changed to enlarge/reduce recognition areas, whereby erroneous recognition is prevented and a recognition rate is improved.
摘要翻译： 本发明涉及一种模式识别系统，其中要被添加的新的参考数据被有效地学习。 在图案识别系统中，执行与图案搜索对象的输入数据和多个参考数据之间的相似度相当的距离的计算，并且基于与参考数据集相对应的固定次数的输入数据作为 计算出其重心，以优化参考数据。 此外，改变阈值以放大/缩小识别区域，从而防止错误识别并提高识别率。
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公开(公告)号：US20080222360A1
公开(公告)日：2008-09-11
申请号：US12034454
申请日：2008-02-20
IPC分类号： G06F12/00
CPC分类号： G06F12/0853 , G06F9/3802 , G06F9/3808 , G06F9/3814 , G06F12/0846 , G06F12/0886
摘要： A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.
摘要翻译： 提供在并行处理器和主存储器之间并存储有存储在主存储器中的指令和数据的一部分的多端口指令/数据集成高速缓存具有多个存储体，并且多个端口包括指令端口单元 由用于访问来自并行处理器的指令的至少一个指令端口和由用于从并行处理器访问数据的至少一个数据端口组成的数据端口单元组成。 此外，可以从指令端口指定给存储体的数据宽度被设置为大于可以从数据端口指定给存储体的数据宽度。
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7.发明授权Image segmentation apparatus, image segmentation method, and image segmentation integrated circuit for processing an image 有权图像分割装置，图像分割方法和用于处理图像的图像分割集成电路公开(公告)号：US07599557B2
公开(公告)日：2009-10-06
申请号：US12098650
申请日：2008-04-07
IPC分类号： G06K9/34
CPC分类号： G06K9/342 , G06K9/00986 , G06T7/11 , G06T7/20 , G06T2200/28 , G06T2207/10016
摘要： In a boundary active only scheme proposed by the present invention, only a cell in a boundary of region growth is brought into an active mode, and the other cells are brought into a standby mode. The respective cells perform state transition in parallel, and decision of the state transition performed for each clock cycle is not performed in a case where any of the three conditions that none of the adjacent cells is ignited, the cell itself is already ignited, and the cell already belongs to a certain divided region is satisfied. Therefore the number of simultaneously operating cells and that of coupling weight registers are minimized, and control is automatically executed to reduce power consumption.
摘要翻译： 在本发明提出的仅边界有效方案中，只有区域增长边界中的单元才能进入活动模式，其他单元进入待机模式。 各个小区并行执行状态转换，并且在没有相邻小区被点燃的三个条件，小区本身已被点燃的情况下，不执行对于每个时钟周期执行的状态转换的判定，并且 细胞已经属于某个分割区域。 因此，同时工作的单元和耦合重量寄存器的数量最小化，自动执行控制以降低功耗。
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公开(公告)号：US20080106469A1
公开(公告)日：2008-05-08
申请号：US10553994
申请日：2004-03-29
申请人： Takamaro Kikkawa , Atsushi Iwata , Hideo Sunami , Hans Jurgen Mattausch , Shin Yokoyama , Kentaro Shibahara , Anri Nakajima , Tetsushi Koide , A.B.M. Harun-ur Rashid , Shinji Watanabe
发明人： Takamaro Kikkawa , Atsushi Iwata , Hideo Sunami , Hans Jurgen Mattausch , Shin Yokoyama , Kentaro Shibahara , Anri Nakajima , Tetsushi Koide , A.B.M. Harun-ur Rashid , Shinji Watanabe
CPC分类号： H01L23/642 , H01L23/48 , H01L23/5227 , H01L2924/0002 , H01Q1/38 , H01L2924/00
摘要： The present invention provides a semiconductor device in which, in order to prevent wiring delay, an electromagnetic wave is radiated from a transmitting dipole antenna placed on a semiconductor chip and received with a receiving antenna placed in a circuit block included in another semiconductor chip, instead of long metal wires or via-hole interconnection. In the semiconductor device, wireless interconnection is accomplished in such a manner that the electromagnetic wave radiated from the transmitting antenna (3) placed on the semiconductor substrate (1) is transmitted to the receiving antenna (4) placed on the semiconductor substrate (1) or receiving antennas placed on semiconductor substrates; the semiconductor substrates have broadband transmitting/receiving antennas; a signal is transmitted from one or more of the semiconductor substrates and received with the receiving antenna or antennas placed on the semiconductor substrate (1) or substrates, respectively; and the signal transmitted and received has an ultra-wide band communication function.
摘要翻译： 本发明提供了一种半导体器件，其中为了防止布线延迟，电磁波从放置在半导体芯片上的发射偶极子天线辐射并且被放置在包含在另一个半导体芯片中的电路块中的接收天线接收 长金属线或通孔互连。 在半导体装置中，以从放置在半导体基板（1）上的发射天线（3）辐射的电磁波传输到放置在半导体基板（1）上的接收天线（4）的方式实现无线互连， 或接收放置在半导体衬底上的天线; 半导体衬底具有宽带发射/接收天线; 从一个或多个半导体衬底发送信号并分别与放置在半导体衬底（1）或衬底上的接收天线或天线一起接收信号; 并且发送和接收的信号具有超宽带通信功能。
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9.发明申请Associative memory apparatus for searching data in which manhattan distance is minimum 有权用于搜索曼哈顿距离最小的数据的关联存储装置公开(公告)号：US20050162878A1
公开(公告)日：2005-07-28
申请号：US10915430
申请日：2004-08-11
申请人： Tetsushi Koide , Hans Mattausch , Yuji Yano
发明人： Tetsushi Koide , Hans Mattausch , Yuji Yano
CPC分类号： G11C15/00
摘要： In the present invention, focusing on the point that the number of transistors can be reduced to about ⅖ of that in a prior art due to an absolute-value-of-difference calculating circuit for an associative memory being configured of an addition circuit and a bit inversion circuit. The absolute-value-of-difference calculating circuit is built in a fully-parallel type associative memory as a unit comparison circuit, and all of the outputs of the absolute-value-of-difference calculating circuits for which the number of comparisons thereof are prepared are input to weight comparison circuits, whereby the calculation of the Manhattan distance between the search data and the reference data is carried out. In accordance with the configuration, because a Manhattan distance calculating circuit can be realized by a fewer number of transistors and with a small area, an associative memory apparatus as well can be realized at a low power consumption and with a small area.
摘要翻译： 在本发明中，由于由联结存储器的差值绝对值计算电路由加法电路构成，因此重点在于现有技术中晶体管的数目可以减少到约2/5， 和位反转电路。 差分绝对值计算电路作为单位比较电路而构成全平行型联想存储器，并且其比较数的差分计算电路的绝对值计算电路的所有输出 准备的输入到加权比较电路，由此执行搜索数据和参考数据之间的曼哈顿距离的计算。 根据该结构，由于可以通过较少数量的晶体管和小面积来实现曼哈顿距离计算电路，所以可以在低功耗和小面积上实现关联存储装置。
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公开(公告)号：US20100189351A1
公开(公告)日：2010-07-29
申请号：US12664946
申请日：2008-07-31
摘要： A dividing unit divides respective symbol sequences of input data applied with zigzag scan and a run-length process into a plurality of subsets having similar frequencies of occurrence, depending on a difference in frequencies of occurrence. A table creating unit scans each subset and creates a Huffman coding table for each subset. A coding unit executes a process for performing Huffman coding on each subset by using the Huffman coding table created for the subset, for all of the subsets in the plurality of subsets.
摘要翻译： 分割单元根据发生频率的差异，将施加有锯齿形扫描和游程长度处理的输入数据的各符号序列分割为具有相似发生频率的多个子集。 表创建单元扫描每个子集，并为每个子集创建霍夫曼编码表。 编码单元通过使用针对该子集创建的霍夫曼编码表，对多个子集中的所有子集执行用于对每个子集执行霍夫曼编码的处理。
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