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6 条记录 (耗时 0.038 秒)

    Dynamic ram
    3.
    发明授权
    Dynamic ram 失效
    动态ram

    公开(公告)号：US4947373A

    公开(公告)日：1990-08-07

    申请号：US134355

    申请日：1987-12-17

    申请人： Yasunori Yamaguchi ,  Katsuyuki Sato ,  Jun Mitake ,  Hitoshi Kawaguchi ,  Masahiro Yoshida ,  Terutaka Okada ,  Makoto Morino ,  Tetsuya Saeki ,  Yosuke Yukawa ,  Osamu Nagashima

    发明人： Yasunori Yamaguchi ,  Katsuyuki Sato ,  Jun Mitake ,  Hitoshi Kawaguchi ,  Masahiro Yoshida ,  Terutaka Okada ,  Makoto Morino ,  Tetsuya Saeki ,  Yosuke Yukawa ,  Osamu Nagashima

    IPC分类号： G11C11/4096

    CPC分类号： G11C11/4096

    摘要： A semiconductor memory is provided with a first memory cell group, a second memory cell group, a first register for a serial output operation for holding information related to the first memory cell group, a second register for a serial output operation for holding information related to the second memory cell group, and transfer means for transferring information related to either the first or second memory cell group to either the first or second serial output register. By virtue of this arrangement, while the information transferred to the first serial output register is being serially output therefrom, information can simultaneously be transferred to the second serial output register by the transfer means.

    摘要翻译： 半导体存储器设置有第一存储单元组，第二存储单元组，用于保持与第一存储单元组相关的信息的串行输出操作的第一寄存器，用于保持与第一存储单元组相关的信息的串行输出操作的第二寄存器 第二存储单元组和用于将与第一或第二存储单元组相关的信息传送到第一或第二串行输出寄存器的传送装置。 通过这种布置，当传送到第一串行输出寄存器的信息正在从其串行输出时，信息可以由传送装置同时传送到第二串行输出寄存器。

    Structure for coupling two types of members
    4.
    发明授权
    Structure for coupling two types of members 有权
    用于耦合两种类型的构件的结构

    公开(公告)号：US06439622B1

    公开(公告)日：2002-08-27

    申请号：US09413015

    申请日：1999-10-06

    申请人： Takane Iwatsuki ,  Tetsuya Saeki

    发明人： Takane Iwatsuki ,  Tetsuya Saeki

    IPC分类号： F01N718

    CPC分类号： F02M35/10144 ,  B29C65/56 ,  B29C65/564 ,  B29C66/1122 ,  B29C66/54 ,  B29C66/55 ,  B29C66/71 ,  B29C66/73112 ,  F02M35/10321 ,  F02M35/1036 ,  F02M35/1255 ,  F02M35/1283 ,  B29K2077/00 ,  B29K2023/12

    摘要： There is difference between coefficients of thermal expansion of the first member and the second member. A mismatch occurs between the walls of the first member and the second member when the temperature is changed significantly. Stress generated by this mismatch is distributed among and received by respective fitting sections of respective concave portions and respective convex portions. Because these fitting sections exist above and below the joining member, stress generated by the mismatch is distributed and received by the fitting sections before the stress reaches the joining member. Therefore, only a little stress acts on the joining member.

    摘要翻译： 第一构件和第二构件的热膨胀系数之间存在差异。 当温度显着变化时，第一构件的壁和第二构件的壁之间发生不匹配。 由这种不匹配产生的应力分布在相应的凹部和相应的凸部​​的各个嵌合部分之间并被其接收。 由于这些装配部分存在于接合部件的上方和下方，所以由应变产生的应力在应力到达接合部件之前由配合部分分配和接收。 因此，只有轻微的压力作用于接合部件。

    Semiconductor memory device and defective memory cell repair circuit
    5.
    发明授权
    Semiconductor memory device and defective memory cell repair circuit 失效
    半导体存储器件和有缺陷的存储器单元修复电路

    公开(公告)号：US5487040A

    公开(公告)日：1996-01-23

    申请号：US90848

    申请日：1993-07-12

    申请人： Shunichi Sukegawa ,  Tetsuya Saeki

    发明人： Shunichi Sukegawa ,  Tetsuya Saeki

    IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L27/10 ,  G11C13/00

    CPC分类号： G11C29/806 ,  G11C29/781

    摘要： To provide a type of semiconductor memory device characterized by the fact that the area occupied by the redundant memory address decoder on the chip is minimized without reducing the redundancy of the defective memory, and hence the cost of the semiconductor memory device can be cut.It has both redundant decoders that select the redundant memory in response to the all address bits and the redundant decoders which select the redundant memory group in response to a portion of the address bits, so as to increase the efficiency in saving the defective memory.

    摘要翻译： 为了提供一种半导体存储器件，其特征在于芯片上的冗余存储器地址解码器占用的面积最小化，而不减少缺陷存储器的冗余，因此可以削减半导体存储器件的成本。 它具有两个冗余解码器，其响应于所有地址位选择冗余存储器，并且响应于一部分地址位选择冗余存储器组的冗余解码器，以便提高保存有缺陷存储器的效率。

    Semiconductor memory device and defective memory cell repair circuit
    6.
    发明授权
    Semiconductor memory device and defective memory cell repair circuit 失效
    半导体存储器件和有缺陷的存储器单元修复电路

    公开(公告)号：US5422850A

    公开(公告)日：1995-06-06

    申请号：US90450

    申请日：1993-07-12

    申请人： Shunichi Sukegawa ,  Tetsuya Saeki

    发明人： Shunichi Sukegawa ,  Tetsuya Saeki

    IPC分类号： G11C29/00 ,  G11C11/40

    CPC分类号： G11C29/70

    摘要： To provide a type of semiconductor memory device characterized by the fact that the redundancy for the defective memory of defective bits is increased and the area occupied by the redundant memory address decoder on the chip is minimized, thereby reducing the cost of the semiconductor memory device. It has multiple fuse decoders which are commonly connected to the address bus and are programmed for the different addresses, and it has a redundant address decoder which detects coincidence/uncoincidence between the outputs of the two decoders and generates a redundant address coincidence signal, so as to increase the efficiency in repairing the defective memory.

    摘要翻译： 为了提供一种半导体存储器件，其特征在于：有缺陷的位的缺陷存储器的冗余增加，芯片上的冗余存储器地址译码器占用的面积最小化，从而降低了半导体存储器件的成本。 它具有多个保险丝解码器，通常连接到地址总线，并被编程用于不同的地址，并且具有冗余地址解码器，其检测两个解码器的输出之间的重合/不一致，并产生冗余地址一致信号，以便 以提高修复缺陷记忆体的效率。