公开(公告)号：US10672475B2

公开(公告)日：2020-06-02

申请号：US16580256

申请日：2019-09-24

申请人： The Penn State Research Foundation

发明人： Xueqing Li ,  Sumitha George ,  John Sampson ,  Sumeet Gupta ,  Suman Datta ,  Vijaykrishnan Narayanan ,  Kaisheng Ma

IPC分类号： G11C14/00 ,  G11C13/00 ,  G11C11/22 ,  H01L29/78 ,  G11C11/16

摘要： Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS−VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.

公开(公告)号：US20180330791A1

公开(公告)日：2018-11-15

申请号：US15976315

申请日：2018-05-10

申请人： The Penn State Research Foundation

发明人： Xueqing Li ,  Sumitha George ,  John Sampson ,  Sumeet Gupta ,  Suman Datta ,  Vijaykrishnan Narayanan ,  Kaisheng Ma

IPC分类号： G11C14/00 ,  H01L29/78 ,  G11C13/00

CPC分类号： G11C14/0072 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/223 ,  G11C11/2275 ,  G11C11/2293 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0061 ,  G11C13/0069 ,  G11C14/0054 ,  G11C14/0081 ,  G11C14/009 ,  H01L29/78391

摘要： Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS−VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.

公开(公告)号：US10475514B2

公开(公告)日：2019-11-12

申请号：US15976315

申请日：2018-05-10

申请人： The Penn State Research Foundation

发明人： Xueqing Li ,  Sumitha George ,  John Sampson ,  Sumeet Gupta ,  Suman Datta ,  Vijaykrishnan Narayanan ,  Kaisheng Ma

IPC分类号： G11C14/00 ,  G11C13/00 ,  H01L29/78 ,  G11C11/16 ,  G11C11/22

摘要： Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS-VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.

公开(公告)号：US10262714B2

公开(公告)日：2019-04-16

申请号：US15614261

申请日：2017-06-05

申请人： The Penn State Research Foundation

发明人： Sumeet Kumar Gupta ,  Ahmedullah Aziz ,  Nikhil Shukla ,  Suman Datta ,  Xueqing Li ,  Vijaykrishnan Narayanan

IPC分类号： G11C11/16 ,  G11C13/00 ,  G11C7/06

摘要： A sense amplifier utilizes a phase transition material (PTM) in conjunction with CMOS circuits to provide a precise sensing threshold. The sense amplifier can be used in memory applications to sense states of stored bits with high accuracy and robustness. In one sense amplifier, a first diode-connected transistor has gate and drain nodes coupled to an input node of the sense amplifier, a second transistor has a gate node coupled to the gate node of the first diode-connected transistor, and the PTM is coupled to the source node of the second transistor. In another sense amplifier, a first transistor has a gate node coupled to an input node of the sense amplifier, a PTM is coupled to the source node of the first transistor, and an output stage including an inverter is coupled between a drain node of the first transistor and an output node of the sense amplifier.

公开(公告)号：US20200027508A1

公开(公告)日：2020-01-23

申请号：US16580256

申请日：2019-09-24

申请人： The Penn State Research Foundation

发明人： Xueqing Li ,  Sumitha George ,  John Sampson ,  Sumeet Gupta ,  Suman Datta ,  Vijaykrishnan Narayanan ,  Kaisheng Ma

IPC分类号： G11C14/00 ,  G11C13/00 ,  G11C11/22 ,  G11C11/16 ,  H01L29/78

摘要： Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS−VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.

公开(公告)号：US09800094B2

公开(公告)日：2017-10-24

申请号：US14712182

申请日：2015-05-14

申请人： The Penn State Research Foundation

发明人： Huichu Liu ,  Ramesh Vaddi ,  Vijaykrishnan Narayanan ,  Suman Datta ,  Moon Seok Kim ,  Xueqing Li ,  Alexandre Schmid ,  Mahsa Shoaran ,  Unsuk Heo

IPC分类号： H01F37/00 ,  H01F38/00 ,  H02J50/20 ,  H02J5/00 ,  H01L29/739

CPC分类号： H02J5/00 ,  H01L29/7391 ,  H02J5/005 ,  H02J7/025 ,  H02J50/20

摘要： Disclosed are low power electronic devices configured to exploit the sub-threshold swing, unidirectional tunneling, and low-voltage operation of steep slope-tunnel tunnel field-effect transistors (TFET) to improve power-conversion efficiency and power-efficiency of electrical systems incorporating the TFET as an electrical component to perform energy harvesting, signal processing, and related operations. The devices include a HTFET-based rectifier having various topologies, a HTFET-based DC-DC charge pump converter, a HTFET-based amplifier having an amplifier circuit including a telescopic operational transconductance amplifier, and a HTFET-based SAR A/D converter having a HTFET-based transmission gate DFF. Any one of the devices may be used to generate a RF-powered system with improved power conversion efficiencies of power harvesters and power efficiencies of processing components within the system.

公开(公告)号：US20150333534A1

公开(公告)日：2015-11-19

申请号：US14712182

申请日：2015-05-14

申请人： The Penn State Research Foundation

发明人： Huichu Liu ,  Ramesh Vaddi ,  Vijaykrishnan Narayanan ,  Suman Datta ,  Moon Seok Kim ,  Xueqing Li ,  Alexandre Schmid ,  Mahsa Shoaran ,  Unsuk Heo

IPC分类号： H02J5/00

CPC分类号： H02J5/00 ,  H01L29/7391 ,  H02J5/005 ,  H02J7/025 ,  H02J50/20

摘要： Disclosed are low power electronic devices configured to exploit the sub-threshold swing, unidirectional tunneling, and low-voltage operation of steep slope-tunnel tunnel field-effect transistors (TFET) to improve power-conversion efficiency and power-efficiency of electrical systems incorporating the TFET as an electrical component to perform energy harvesting, signal processing, and related operations. The devices include a HTFET-based rectifier having various topologies, a HTFET-based DC-DC charge pump converter, a HTFET-based amplifier having an amplifier circuit including a telescopic operational transconductance amplifier, and a HTFET-based SAR A/D converter having a HTFET-based transmission gate DFF. Any one of the devices may be used to generate a RF-powered system with improved power conversion efficiencies of power harvesters and power efficiencies of processing components within the system.

摘要翻译： 公开了被配置为利用陡坡隧道场效应晶体管（TFET）的亚阈值摆幅，单向隧道和低电压操作的低功率电子器件，以提高并入电气系统的电力转换效率和功率效率 TFET作为执行能量收集，信号处理和相关操作的电气部件。 这些器件包括具有各种拓扑结构的基于HTFET的整流器，基于HTFET的DC-DC电荷泵转换器，具有包括可伸缩运算跨导放大器的放大器电路的基于HTFET的放大器，以及基于HTFET的SAR A / D转换器， 一个基于HTFET的传输门DFF。 可以使用任何一个设备来生成具有改进的功率收集器的功率转换效率和系统内处理组件的功率效率的RF供电的系统。