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1.
公开(公告)号:US09448879B2
公开(公告)日:2016-09-20
申请号:US13994105
申请日:2011-12-22
申请人: Theodros Yigzaw , Oded Lempel , Hisham Shafi , Geeyarpuram N. Santhanakrishnan , Jose A. Vargas , Ganapati N Srinivasa , Mohan J Kumar , Larisa Novakovsky , Lihu Rappoport , Chen Koren , Julius Mandelblat , Michael Mishaeli
发明人: Theodros Yigzaw , Oded Lempel , Hisham Shafi , Geeyarpuram N. Santhanakrishnan , Jose A. Vargas , Ganapati N Srinivasa , Mohan J Kumar , Larisa Novakovsky , Lihu Rappoport , Chen Koren , Julius Mandelblat , Michael Mishaeli
CPC分类号: G06F11/1064 , G06F11/0793 , G06F11/1016 , G06F11/1407
摘要: An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.
摘要翻译: 描述了用于检测和校正处理器核心内的指令获取错误的装置和方法。 例如,在一个实施例中,用于从指令获取错误中检测和恢复的指令处理装置包括:指令处理装置执行以下操作:响应于指令提取操作检测与指令相关联的错误; 以及确定所述指令是否来自投机访问,其中如果所述指令不是来自投机访问,则响应地执行一个或多个操作以确保所述错误不会破坏所述处理器核心的架构状态。
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2.
公开(公告)号:US20140298140A1
公开(公告)日:2014-10-02
申请号:US13994105
申请日:2011-12-22
申请人: Theodros Yigzaw , Oded Lempel , Hisham Hafi , Geeyarpuram N Santhanakrisnan , Jose A Vargas , Ganapati N Srinivasa , Mohan J Kumar , Larisa Novakovsky , Lihu Rappoport , Chen Koren , Julius Yuli Mandelblat
发明人: Theodros Yigzaw , Oded Lempel , Hisham Hafi , Geeyarpuram N Santhanakrisnan , Jose A Vargas , Ganapati N Srinivasa , Mohan J Kumar , Larisa Novakovsky , Lihu Rappoport , Chen Koren , Julius Yuli Mandelblat
IPC分类号: G06F11/10
CPC分类号: G06F11/1064 , G06F11/0793 , G06F11/1016 , G06F11/1407
摘要: An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.
摘要翻译: 描述了用于检测和校正处理器核心内的指令获取错误的装置和方法。 例如,在一个实施例中,用于从指令获取错误中检测和恢复的指令处理装置包括:指令处理装置执行以下操作:响应于指令获取操作检测与指令相关联的错误; 以及确定所述指令是否来自投机访问,其中如果所述指令不是来自投机访问,则响应地执行一个或多个操作以确保所述错误不会破坏所述处理器核心的架构状态。
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