公开(公告)号：US20050050505A1

公开(公告)日：2005-03-03

申请号：US10604995

申请日：2003-08-29

申请人： Thomas Bednar ,  Timothy Budell ,  Patrick Buffet ,  Alain Caron ,  James Crain ,  Douglas Kemerer ,  Donald Kent ,  Esmaeil Rahmati

发明人： Thomas Bednar ,  Timothy Budell ,  Patrick Buffet ,  Alain Caron ,  James Crain ,  Douglas Kemerer ,  Donald Kent ,  Esmaeil Rahmati

IPC分类号： H01L23/528 ,  G06F17/50 ,  H01L23/52

CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit chip (104) having a contact layer (136) that includes a plurality of Vdd, Vddx, ground and I/O contacts (116, 120, 124, 128) arranged in a generally radial pattern having diagonal and major axis symmetry and generally defining four quadrants. An X-Y power grid (140) is located beneath the contact layer and includes metal layers (LM′) each having a plurality of wires (68) extending in one direction. The direction of the wires alternates from one metal layer to the next adjacent metal layer. A wiring layer (IM) is interposed between the contact layer and power grid layers to provide a well-behaved electrical transition between the generally radial Vdd, Vddx and ground contacts and the rectangular X-Y power grid. The interposed wiring layer includes concentric square rings of Vdd, Vddx and ground wires (144, 148, 152) located alternatingly with one another. The Vddx wires are discontinuous between adjacent quadrants so that the magnitude of Vddx may be different in each quadrant of the chip if desired.

摘要翻译： 一种具有接触层（136）的集成电路芯片（104），该接触层包括多个Vdd，Vddx，接地和I / O触点（116,120,124,128），其以大致径向图案布置，具有对角线和长轴对称 并通常定义四个象限。 X-Y电网（140）位于接触层下方，并且包括金属层（LM'），每个金属层具有沿一个方向延伸的多根电线（68）。 线的方向从一个金属层交替到下一个相邻的金属层。 在接触层和电网层之间插入布线层（IM），以在大致径向的Vdd，Vddx和接地触头与矩形X-Y电网之间提供良好的电气转变。 插入的布线层包括彼此交替布置的Vdd，Vddx和接地线（144,148,152）的同心方形环。 Vddx线在相邻象限之间是不连续的，使得如果需要，Vddx的幅度可以在芯片的每个象限中不同。

公开(公告)号：US20060036981A1

公开(公告)日：2006-02-16

申请号：US11234560

申请日：2005-09-23

申请人： Timothy Budell ,  Patrick Buffet ,  Craig Lussier

发明人： Timothy Budell ,  Patrick Buffet ,  Craig Lussier

IPC分类号： G06F17/50

CPC分类号： G01R31/2853 ,  G01R31/2896 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/065 ,  G06F3/067 ,  G06F11/2069

摘要： An electrical resistance determination method. Input to the method includes a description of at least one electrical network within a substrate. The description includes specification of a plurality of first ports on a first side of the substrate, and a plurality of second ports on a second side of the substrate, for each electrical network. All of the first ports are electrically isolated from one another. All of the second ports are electrically connected to a common voltage. A computer readable program code, which is executed by a processor of a computer system computes for a first electrical network of the at least one electrical network an electrical resistance between each first port and a port of the second ports. The computer code may also display a perspective plot of the computed electrical resistances as a bar oriented about normal to each first port.

摘要翻译： 电阻测定方法。 该方法的输入包括对衬底内的至少一个电网的描述。 该描述包括对于每个电网络，在衬底的第一侧上的多个第一端口以及衬底的第二侧上的多个第二端口的规格。 所有的第一个端口彼此电隔离。 所有第二端口电连接到公共电压。 由计算机系统的处理器执行的计算机可读程序代码为所述至少一个电网的第一电网计算每个第一端口和第二端口的端口之间的电阻。 计算机代码还可以将所计算的电阻的透视图显示为大致垂直于每个第一端口的条。

公开(公告)号：US20050114050A1

公开(公告)日：2005-05-26

申请号：US10721966

申请日：2003-11-25

申请人： Timothy Budell ,  Patrick Buffet ,  Craig Lussier

发明人： Timothy Budell ,  Patrick Buffet ,  Craig Lussier

IPC分类号： G01R31/04 ,  G01R31/28 ,  G06F3/06 ,  G06F11/00 ,  G06F11/14 ,  G06F11/20 ,  G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G06F19/00

CPC分类号： G01R31/2853 ,  G01R31/2896 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/065 ,  G06F3/067 ,  G06F11/2069

摘要： An electrical resistance determination method. Input to the method includes a description of at least one electrical network within a substrate. The description includes specification of a plurality of first ports on a first side of the substrate, and a plurality of second ports on a second side of the substrate, for each electrical network. All of the first ports are electrically isolated from one another. All of the second ports are electrically connected to a common voltage. A computer readable program code, which is executed by a processor of a computer system computes for a first electrical network of the at least one electrical network an electrical resistance between each first port and a port of the second ports. The computer code may also display a perspective plot of the computed electrical resistances as a bar oriented about normal to each first port.

摘要翻译： 电阻测定方法。 该方法的输入包括对衬底内的至少一个电网的描述。 该描述包括对于每个电网络，在衬底的第一侧上的多个第一端口以及衬底的第二侧上的多个第二端口的规格。 所有的第一个端口彼此电隔离。 所有第二端口电连接到公共电压。 由计算机系统的处理器执行的计算机可读程序代码为所述至少一个电网的第一电网计算每个第一端口和第二端口的端口之间的电阻。 计算机代码还可以将所计算的电阻的透视图显示为大致垂直于每个第一端口的条。

公开(公告)号：US20080010625A1

公开(公告)日：2008-01-10

申请号：US11858995

申请日：2007-09-21

申请人： Adam Bittner ,  Timothy Budell ,  Robert Cusimano ,  Richard Dauphin ,  Matthew Guzowski ,  Craig Lussier ,  David Stone ,  Patrick Wilder

发明人： Adam Bittner ,  Timothy Budell ,  Robert Cusimano ,  Richard Dauphin ,  Matthew Guzowski ,  Craig Lussier ,  David Stone ,  Patrick Wilder

IPC分类号： G06F17/50

CPC分类号： H01L23/50 ,  G06F17/5077 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011

摘要： A system and method for generating simulated wiring connections between a semiconductor device and a carrier. The method comprises identifying a plurality of first factors and instances of each first factor relating to the semiconductor device and identifying a plurality of second factors and instances of each second factor relating to the carrier. The first and second factors are associated with each other on a one-to-one basis. A simulated wiring connection is generated between a first I/O terminal and a matching second I/O terminal, subject to an identified instance of each first factor of each first I/O terminal being correlated to an identified instance of the associated second factor of the matching second I/O terminal. A simulated wiring connection is generated between third I/O terminals located in a first region and fourth I/O terminals located in said second region.

摘要翻译： 一种用于在半导体器件和载体之间产生模拟布线连接的系统和方法。 该方法包括识别与半导体器件相关的多个第一因子和每个第一因素的实例，并且识别与载波相关的每个第二因素的多个第二因素和实例。 第一和第二因素在一对一的基础上相互关联。 在第一I / O端子和匹配的第二I / O端子之间产生模拟接线连接，受到每个第一I / O端子的每个第一因子的识别实例与所识别的相关联的第二因子的实例相关联 匹配的第二个I / O终端。 在位于第一区域的第三I / O端子和位于所述第二区域中的第四I / O端子之间产生模拟布线连接。

公开(公告)号：US20060047490A1

公开(公告)日：2006-03-02

申请号：US10711168

申请日：2004-08-30

申请人： Erik Breiland ,  Timothy Budell ,  Charles Chiu ,  Paul Clouser ,  Charles Erdelyi ,  Brian Welch

发明人： Erik Breiland ,  Timothy Budell ,  Charles Chiu ,  Paul Clouser ,  Charles Erdelyi ,  Brian Welch

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/78

摘要： The invention relates generally to a method of power supply noise and signal integrity analysis for creating frequency-dependent electrical models particularly related to microelectronic packages. The method discloses creation of equivalent circuits for geometries encountered in a typical chip package, including how to partition the geometry into cells which are less then 1/20 the minimum wavelength (λ) in size, and how to handle signal and power supply vias, signal wires, and power planes. The method also instructs how to assign values to each of the inductors, capacitors, resistors, and transmission lines in each equivalent circuit. The method further provides modeling of only those interactions which occur between adjacent cells.

摘要翻译： 本发明一般涉及一种用于产生与微电子封装特别相关的频率相关的电气模型的电源噪声和信号完整性分析方法。 该方法公开了在典型芯片封装中遇到的几何形状的等效电路的创建，包括如何将几何划分成小于小于最小波长（λ）的1/20的单元，以及如何处理信号和电源通孔， 信号线和电源平面。 该方法还指示如何为每个等效电路中的每个电感器，电容器，电阻器和传输线分配值。 该方法还提供仅在相邻小区之间发生的那些相互作用的建模。

公开(公告)号：US20050176273A1

公开(公告)日：2005-08-11

申请号：US10776737

申请日：2004-02-10

申请人： Timothy Budell ,  Eric Tremble ,  Brian Welch

发明人： Timothy Budell ,  Eric Tremble ,  Brian Welch

IPC分类号： H01L23/498 ,  H01L23/50 ,  H01R12/00

CPC分类号： H01L23/49838 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/15159 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011

摘要： The present invention provides a redistribution package having an upper surface that includes contacts with reduced pitch that correspond, for example, to that of a Controlled Collapse Chip Connection (“C4”) structure formed on a chip, and a lower surface having contacts with increased pitch that correspond, for example, to a printed circuit board employing ball grid array (“BGA”) pads. A series of power, signal and ground conductors extend through the body of the redistribution package and interconnect the circuit board contacts to the chip contacts.

摘要翻译： 本发明提供一种再分配封装，其具有上表面，该上表面包括减小的间距的触点，例如与形成在芯片上的受控塌陷芯片连接（“C4”）结构对应，并且具有增加的触点的下表面 间距，例如对应于使用球栅阵列（“BGA”）焊盘的印刷电路板。 一系列电源，信号和接地导体延伸穿过再分配封装的主体，并将电路板触点与芯片触点相互连接。

公开(公告)号：US20060294487A1

公开(公告)日：2006-12-28

申请号：US11159915

申请日：2005-06-23

申请人： Adam Bittner ,  Timothy Budell ,  Robert Cusimano ,  Richard Dauphin ,  Matthew Guzowski ,  Craig Lussier ,  David Stone ,  Patrick Wilder

发明人： Adam Bittner ,  Timothy Budell ,  Robert Cusimano ,  Richard Dauphin ,  Matthew Guzowski ,  Craig Lussier ,  David Stone ,  Patrick Wilder

IPC分类号： G06F17/50

CPC分类号： H01L23/50 ,  G06F17/5077 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011

摘要： A system and method for generating simulated wiring connections between first I/O terminals of a semiconductor device and second I/O terminals of a carrier. The method comprises identifying a plurality of first factors and instances of each first factor relating to a semiconductor device and identifying a plurality of second factors and instances of each second factor relating to a carrier. The first and second factors are associated with each other on a one-to-one basis. The instances of each first factor are correlated to the instances of each associated second factor on a one-to-one basis. A simulated wiring connection automatically is generated between each first I/O terminal and a matching second I/O terminal, subject to an identified instance of each first factor of each first I/O terminal being correlated to an identified instance of the associated second factor of the matching second I/O terminal.

摘要翻译： 一种用于在半导体器件的第一I / O端子与载体的第二I / O端子之间产生模拟布线连接的系统和方法。 该方法包括识别与半导体器件相关的每个第一因素的多个第一因素和实例，并且识别与载波相关的每个第二因素的多个第二因素和实例。 第一和第二因素在一对一的基础上相互关联。 每个第一因子的实例与每个相关联的第二因子的实例在一对一的基础上相关。 在每个第一I / O终端和匹配的第二I / O终端之间自动生成模拟接线连接，受到每个第一I / O端子的每个第一因子的识别实例与相关联的第二因素的识别实例相关联 的匹配第二个I / O端子。

公开(公告)号：US20060108142A1

公开(公告)日：2006-05-25

申请号：US11251745

申请日：2005-10-17

申请人： Timothy Budell ,  Thomas Comino ,  Todd Davies ,  Ross Keesler ,  Steven Rosser ,  David Stone

发明人： Timothy Budell ,  Thomas Comino ,  Todd Davies ,  Ross Keesler ,  Steven Rosser ,  David Stone

IPC分类号： H05K1/00

CPC分类号： H05K1/0224 ,  H05K1/0253 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09672 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2203/1178 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

摘要： A method, structure, and method of design relating an electrical structure that includes a metal voltage plane laminated to a dielectric substrate. A determination is made as to where to place an opening for venting gases generated during fabrication of the dielectric laminate. An identification is made of a problematic opening in the metal voltage plane that is above or below a corresponding metal signal line within the dielectric laminate, such that an image of a portion of the corresponding metal signal line projects across the problematic opening. An electrically conductive strip is positioned across the problematic opening, such that the strip includes the image. In fabrication, the dielectric substrate having the metal signal line therein is provided. The metal voltage plane is laminated to the dielectric substrate. The opening in the metal voltage plane is formed such that the strip is across the opening and includes the image.