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    Delta-doped hybrid advanced detector for low energy particle detection
    3.
    发明授权
    Delta-doped hybrid advanced detector for low energy particle detection 有权
    用于低能量粒子检测的三角混合高级检测器

    公开(公告)号：US06346700B1

    公开(公告)日：2002-02-12

    申请号：US09546837

    申请日：2000-04-11

    申请人： Thomas J. Cunningham ,  Eric R. Fossum ,  Shouleh Nikzad ,  Bedabrata Pain ,  George A. Soli

    发明人： Thomas J. Cunningham ,  Eric R. Fossum ,  Shouleh Nikzad ,  Bedabrata Pain ,  George A. Soli

    IPC分类号： H01L3100

    CPC分类号： H01L27/14634

    摘要： A delta-doped hybrid advanced detector (HAD) is provided which combines at least four types of technologies to create a detector for energetic particles ranging in energy from hundreds of electron volts (eV) to beyond several million eV. The detector is sensitive to photons from visible light to X-rays. The detector is highly energy-sensitive from approximately 10 keV down to hundreds of eV. The detector operates with milliwatt power dissipation, and allows non-sequential readout of the array, enabling various advanced readout schemes.

    摘要翻译： 提供了一种三角掺杂混合高级检测器（HAD），其结合了至少四种类型的技术，以产生能量范围从几百电子伏特（eV）到超过几百万eV的能量粒子的检测器。 检测器对从可见光到X射线的光子敏感。 检测器对大约10keV到几百eV的高能量敏感性。 该检测器以毫瓦功率消耗运行，并允许阵列的非顺序读出，实现各种先进的读出方案。

    Increasing the dynamic range of CMOS photodiode imagers
    5.
    发明授权
    Increasing the dynamic range of CMOS photodiode imagers 有权
    增加CMOS光电二极管成像器的动态范围

    公开(公告)号：US07235771B2

    公开(公告)日：2007-06-26

    申请号：US11191603

    申请日：2005-07-27

    申请人： Bedabrata Pain ,  Thomas J. Cunningham ,  Bruce R. Hancock

    发明人： Bedabrata Pain ,  Thomas J. Cunningham ,  Bruce R. Hancock

    IPC分类号： H01L27/00

    CPC分类号： H04N5/3745 ,  H04N5/3559 ,  H04N5/363

    摘要： A multiple-step reset process and circuit for resetting a voltage stored on a photodiode of an imaging device. A first stage of the reset occurs while a source and a drain of a pixel source-follower transistor are held at ground potential and the photodiode and a gate of the pixel source-follower transistor are charged to an initial reset voltage having potential less that of a supply voltage. A second stage of the reset occurs after the initial reset voltage is stored on the photodiode and the gate of the pixel source-follower transistor and the source and drain voltages of the pixel source-follower transistor are released from ground potential thereby allowing the source and drain voltages of the pixel source-follower transistor to assume ordinary values above ground potential and resulting in a capacitive feed-through effect that increases the voltage on the photodiode to a value greater than the initial reset voltage.

    摘要翻译： 一种用于重置存储在成像装置的光电二极管上的电压的多级复位处理和电路。 复位的第一阶段发生在像素源跟随器晶体管的源极和漏极保持在接地电位的同时，并且像素源极跟随器晶体管的光电二极管和栅极被充电到具有小于 电源电压。 复位的第二阶段在初始复位电压存储在光电二极管上并且像素源跟随器晶体管的栅极和像素源极 - 跟随器晶体管的源极和漏极电压从地电位释放之后发生，从而允许源极和源极 像素源极 - 跟随器晶体管的漏极电压将呈现高于地电位的普通值，并产生将光电二极管上的电压增加到大于初始复位电压的值的电容馈通效应。

    High-speed on-chip windowed centroiding using photodiode-based CMOS imager
    6.
    发明授权
    High-speed on-chip windowed centroiding using photodiode-based CMOS imager 有权
    使用基于光电二极管的CMOS成像器的高速片上窗口重心

    公开(公告)号：US06721464B2

    公开(公告)日：2004-04-13

    申请号：US10336701

    申请日：2003-01-03

    申请人： Bedabrata Pain ,  Chao Sun ,  Guang Yang ,  Thomas J. Cunningham ,  Bruce Hancock

    发明人： Bedabrata Pain ,  Chao Sun ,  Guang Yang ,  Thomas J. Cunningham ,  Bruce Hancock

    IPC分类号： G06K920

    CPC分类号： H04N5/374 ,  G06T5/20 ,  G06T7/66 ,  H04N5/3597 ,  H04N5/363

    摘要： A centroid computation system is disclosed. The system has an imager array, a switching network, computation elements, and a divider circuit. The imager array has columns and rows of pixels. The switching network is adapted to receive pixel signals from the image array. The plurality of computation elements operates to compute inner products for at least x and y centroids. The plurality of computation elements has only passive elements to provide inner products of pixel signals the switching network. The divider circuit is adapted to receive the inner products and compute the x and y centroids.

    摘要翻译： 公开了一种质心计算系统。 该系统具有成像器阵列，交换网络，计算元件和分频器电路。 成像器阵列具有列和像素行。 交换网络适于接收来自图像阵列的像素信号。 多个计算元素用于计算至少x和y个质心的内积。 多个计算元件仅具有无源元件以提供交换网络的像素信号的内积。 分频器电路适于接收内部产品并计算x和y重心。

    High-speed on-chip windowed centroiding using photodiode-based CMOS imager
    7.
    发明授权
    High-speed on-chip windowed centroiding using photodiode-based CMOS imager 有权
    使用基于光电二极管的CMOS成像器的高速片上窗口重心

    公开(公告)号：US06519371B1

    公开(公告)日：2003-02-11

    申请号：US09677972

    申请日：2000-10-02

    申请人： Bedabrata Pain ,  Chao Sun ,  Guang Yang ,  Thomas J. Cunningham ,  Bruce Hancock

    发明人： Bedabrata Pain ,  Chao Sun ,  Guang Yang ,  Thomas J. Cunningham ,  Bruce Hancock

    IPC分类号： G06K936

    CPC分类号： H04N5/374 ,  G06T5/20 ,  G06T7/66 ,  H04N5/3597 ,  H04N5/363

    摘要： A centroid computation system is disclosed. The system has an imager array, a switching network, computation elements, and a divider circuit. The imager array has columns and rows of pixels. The switching network is adapted to receive pixel signals from the image array. The plurality of computation elements operates to compute inner products for at least x and y centroids. The plurality of computation elements has only passive elements to provide inner products of pixel signals the switching network. The divider circuit is adapted to receive the inner products and compute the x and y centroids.

    摘要翻译： 公开了一种质心计算系统。 该系统具有成像器阵列，交换网络，计算元件和分频器电路。 成像器阵列具有列和像素行。 交换网络适于接收来自图像阵列的像素信号。 多个计算元素用于计算至少x和y个质心的内积。 多个计算元件仅具有无源元件以提供交换网络的像素信号的内积。 分频器电路适于接收内部产品并计算x和y重心。

    Parallel phase-sensitive three-dimensional imaging camera
    8.
    发明授权
    Parallel phase-sensitive three-dimensional imaging camera 有权
    平行相敏三维成像相机

    公开(公告)号：US07274815B1

    公开(公告)日：2007-09-25

    申请号：US10681961

    申请日：2003-10-09

    申请人： Colin L. Smithpeter ,  Eddie R. Hoover ,  Bedabrata Pain ,  Bruce R. Hancock ,  Robert O. Nellums

    发明人： Colin L. Smithpeter ,  Eddie R. Hoover ,  Bedabrata Pain ,  Bruce R. Hancock ,  Robert O. Nellums

    IPC分类号： G06K9/00

    CPC分类号： G06K9/2036

    摘要： An apparatus is disclosed for generating a three-dimensional (3-D) image of a scene illuminated by a pulsed light source (e.g. a laser or light-emitting diode). The apparatus, referred to as a phase-sensitive 3-D imaging camera utilizes a two-dimensional (2-D) array of photodetectors to receive light that is reflected or scattered from the scene and processes an electrical output signal from each photodetector in the 2-D array in parallel using multiple modulators, each having inputs of the photodetector output signal and a reference signal, with the reference signal provided to each modulator having a different phase delay. The output from each modulator is provided to a computational unit which can be used to generate intensity and range information for use in generating a 3-D image of the scene. The 3-D camera is capable of generating a 3-D image using a single pulse of light, or alternately can be used to generate subsequent 3-D images with each additional pulse of light.

    摘要翻译： 公开了一种用于产生由脉冲光源（例如，激光或发光二极管）照射的场景的三维（3-D）图像的装置。 被称为相敏三维成像相机的装置利用二维（2-D）阵列的光电检测器来接收从场景反射或散射的光，并处理来自每个光电检测器的电输出信号 使用多个调制器并联的2-D阵列，每个调制器具有光电检测器输出信号和参考信号的输入，参考信号提供给具有不同相位延迟的每个调制器。 来自每个调制器的输出被提供给计算单元，该计算单元可用于生成用于生成场景的3-D图像的强度和范围信息。 3-D相机能够使用单个脉冲光产生3-D图像，或者可替代地用于产生具有每个附加脉冲光的随后的3-D图像。

    Nano-multiplication region avalanche photodiodes and arrays
    10.
    发明授权
    Nano-multiplication region avalanche photodiodes and arrays 有权
    纳米倍增区雪崩光电二极管和阵列

    公开(公告)号：US07928533B2

    公开(公告)日：2011-04-19

    申请号：US12191843

    申请日：2008-08-14

    申请人： Xinyu Zheng ,  Bedabrata Pain ,  Thomas J. Cunningham

    发明人： Xinyu Zheng ,  Bedabrata Pain ,  Thomas J. Cunningham

    IPC分类号： H01L29/66

    CPC分类号： H01L31/107 ,  G01J1/42 ,  G01J1/44 ,  H01L27/14643

    摘要： An avalanche photodiode with a nano-scale reach-through structure comprising n-doped and p-doped regions, formed on a silicon island on an insulator, so that the avalanche photodiode may be electrically isolated from other circuitry on other silicon islands on the same silicon chip as the avalanche photodiode. For some embodiments, multiplied holes generated by an avalanche reduces the electric field in the depletion region of the n-doped and p-doped regions to bring about self-quenching of the avalanche photodiode. Other embodiments are described and claimed.

    摘要翻译： 一种具有纳米尺度到达结构的雪崩光电二极管，其包括形成在绝缘体上的硅岛上的n掺杂和p掺杂区域，使得雪崩光电二极管可以与其上的其他硅岛上的其它电路电隔离 硅片作为雪崩光电二极管。 对于一些实施例，由雪崩产生的倍增空穴减小了n掺杂区域和p掺杂区域的耗尽区域中的电场，以引起雪崩光电二极管的自熄。 描述和要求保护其他实施例。