公开(公告)号：US08866227B2

公开(公告)日：2014-10-21

申请号：US13607743

申请日：2012-09-09

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L21/77 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8234

CPC分类号： H01L21/84 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/77 ,  H01L21/823412 ,  H01L27/092

摘要： A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.

摘要翻译： 一种制造半导体器件的方法，其可以从提供半导体衬底开始，所述半导体衬底包括与掩埋电介质层直接接触的包含硅层的第一器件区域，包括与所述掩埋电介质层直接接触的硅锗层的第二器件区域 以及掺杂有碳层的硅的第三器件区域。 然后可以在半导体衬底的第一器件区域内的硅层上形成至少一个低功率半导体器件。 可以在半导体衬底的第二器件区域的硅锗层上形成至少一个p型半导体器件。 可以在半导体衬底的第三器件区域的掺杂有碳层的硅上形成至少一个n型半导体器件。

公开(公告)号：US20130099319A1

公开(公告)日：2013-04-25

申请号：US13607743

申请日：2012-09-09

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/77 ,  H01L21/823412 ,  H01L27/092

摘要： A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.

摘要翻译： 一种制造半导体器件的方法，其可以从提供半导体衬底开始，所述半导体衬底包括与掩埋电介质层直接接触的包含硅层的第一器件区域，包括与所述掩埋电介质层直接接触的硅锗层的第二器件区域 以及掺杂有碳层的硅的第三器件区域。 然后可以在半导体衬底的第一器件区域内的硅层上形成至少一个低功率半导体器件。 可以在半导体衬底的第二器件区域的硅锗层上形成至少一个p型半导体器件。 可以在半导体衬底的第三器件区域的掺杂有碳层的硅上形成至少一个n型半导体器件。

公开(公告)号：US20130099318A1

公开(公告)日：2013-04-25

申请号：US13280850

申请日：2011-10-25

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L27/092 ,  H01L21/20

CPC分类号： H01L21/84 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/77 ,  H01L21/823412 ,  H01L27/092

摘要： A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.

公开(公告)号：US20110175166A1

公开(公告)日：2011-07-21

申请号：US12689339

申请日：2010-01-19

申请人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L27/12 ,  H01L21/782

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/7849

摘要： A semiconductor device and fabrication method include a strained semiconductor layer having a strain in one axis. A long fin and a short fin are formed in the semiconductor layer such that the long fin has a strained length along the one axis. An n-type transistor is formed on the long fin, and a p-type transistor is formed on the at least one short fin. The strain in the n-type transistor improves performance.

摘要翻译： 半导体器件和制造方法包括在一个轴上具有应变的应变半导体层。 在半导体层中形成长鳍片和短鳍片，使得长鳍片沿着一个轴线具有应变长度。 在长鳍片上形成n型晶体管，在该至少一个短鳍片上形成p型晶体管。 n型晶体管中的应变提高了性能。

公开(公告)号：US08169025B2

公开(公告)日：2012-05-01

申请号：US12689339

申请日：2010-01-19

申请人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L27/12

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/7849

摘要： A semiconductor device and fabrication method include a strained semiconductor layer having a strain in one axis. A long fin and a short fin are formed in the semiconductor layer such that the long fin has a strained length along the one axis. An n-type transistor is formed on the long fin, and a p-type transistor is formed on the at least one short fin. The strain in the n-type transistor improves performance.

摘要翻译： 半导体器件和制造方法包括在一个轴上具有应变的应变半导体层。 在半导体层中形成长鳍片和短鳍片，使得长鳍片沿着一个轴线具有应变长度。 在长鳍片上形成n型晶体管，在该至少一个短鳍片上形成p型晶体管。 n型晶体管中的应变提高了性能。

公开(公告)号：US20130193483A1

公开(公告)日：2013-08-01

申请号：US13359858

申请日：2012-01-27

申请人： Stephen W. Bedell ,  Kangguo Cheng ,  Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Kangguo Cheng ,  Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L29/41783 ,  H01L29/7848

摘要： MOSFET structures are provided having a compressively strained silicon channel. A semiconductor device is provided that comprises a field effect transistor (FET) structure having a gate stack on a silicon substrate, wherein the field effect transistor structure comprises a channel formed below the gate stack; and a compressively strained silicon layer on at least a portion of the silicon substrate to compressively strain the channel.

摘要翻译： 提供具有压缩应变硅通道的MOSFET结构。 提供一种半导体器件，其包括在硅衬底上具有栅极堆叠的场效应晶体管（FET）结构，其中所述场效应晶体管结构包括形成在所述栅极堆叠下方的沟道; 以及在所述硅衬底的至少一部分上的压缩应变硅层，以压缩所述通道。

公开(公告)号：US20110263104A1

公开(公告)日：2011-10-27

申请号：US12766859

申请日：2010-04-24

申请人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L21/20

CPC分类号： H01L29/66628 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/78696

摘要： A method for fabricating an FET device is disclosed. The method includes providing a body over an insulator, with the body having at least one surface adapted to host a device channel. Selecting the body to be Si, Ge, or their alloy mixtures. Choosing the body layer to be less than a critical thickness defined as the thickness where agglomeration may set in during a high temperature processing. Such critical thickness may be about 4 nm for a planar devices, and about 8 nm for a non-planar devices. The method further includes clearing surfaces of oxygen at low temperature, and forming a raised source/drain by selective epitaxy while using the cleared surfaces for seeding. After the clearing of the surfaces of oxygen, and before the selective epitaxy, oxygen exposure of the cleared surfaces is being prevented.

摘要翻译： 公开了一种用于制造FET器件的方法。 该方法包括在绝缘体上提供主体，其中主体具有适于承载设备通道的至少一个表面。 选择身体为Si，Ge或其合金混合物。 选择体层小于临界厚度，其临界厚度定义为在高温加工过程中聚集的厚度。 这种临界厚度对于平面器件可以是约4nm，对于非平面器件而言约8nm。 该方法还包括在低温下清除氧的表面，并且通过选择性外延形成凸起的源极/漏极，同时使用清除的表面进行接种。 在氧的表面清除之后，并且在选择性外延之前，防止了清除的表面的氧曝光。

公开(公告)号：US08263468B2

公开(公告)日：2012-09-11

申请号：US12766859

申请日：2010-04-24

申请人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L21/336

CPC分类号： H01L29/66628 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/78696

摘要： A method for fabricating an FET device is disclosed. The method includes providing a body over an insulator, with the body having at least one surface adapted to host a device channel. Selecting the body to be Si, Ge, or their alloy mixtures. Choosing the body layer to be less than a critical thickness defined as the thickness where agglomeration may set in during a high temperature processing. Such critical thickness may be about 4 nm for a planar devices, and about 8 nm for a non-planar devices. The method further includes clearing surfaces of oxygen at low temperature, and forming a raised source/drain by selective epitaxy while using the cleared surfaces for seeding. After the clearing of the surfaces of oxygen, and before the selective epitaxy, oxygen exposure of the cleared surfaces is being prevented.

摘要翻译： 公开了一种用于制造FET器件的方法。 该方法包括在绝缘体上提供主体，其中主体具有适于承载设备通道的至少一个表面。 选择身体为Si，Ge或其合金混合物。 选择体层小于临界厚度，其临界厚度定义为在高温加工过程中聚集的厚度。 这种临界厚度对于平面器件可以是约4nm，对于非平面器件而言约8nm。 该方法还包括在低温下清除氧的表面，并且通过选择性外延形成凸起的源极/漏极，同时使用清除的表面进行接种。 在氧的表面清除之后，并且在选择性外延之前，防止了清除的表面的氧曝光。

公开(公告)号：US20120009766A1

公开(公告)日：2012-01-12

申请号：US12830626

申请日：2010-07-06

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L21/20

CPC分类号： H01L29/1054 ,  H01L29/7833

摘要： A method of forming a strained semiconductor-on-insulator (SSOI) substrate that does not include wafer bonding is provided. In this disclosure a relaxed and doped silicon layer is formed on an upper surface of a silicon-on-insulator (SOI) substrate. In one embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is smaller than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is smaller than the in-plane lattice parameter of the underlying SOI layer. In another embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is larger than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is larger than the in-plane lattice parameter of the underlying SOI layer. After forming the relaxed and doped silicon layer on the SOI substrate, the dopant within the relaxed and doped silicon layer is removed from that layer converting the relaxed and doped silicon layer into a strained (compressively or tensilely) silicon layer that is formed on an upper surface of an SOI substrate.

摘要翻译： 提供了一种形成不包括晶片接合的应变绝缘体上半导体（SSOI）衬底的方法。 在本公开中，在绝缘体上硅（SOI）衬底的上表面上形成松弛和掺杂的硅层。 在一个实施例中，松弛和掺杂硅层内的掺杂剂具有小于硅的原子尺寸的原子尺寸，因此松弛和掺杂硅层的面内晶格参数小于硅的原子尺寸， 下层SOI层的平面晶格参数。 在另一实施例中，松弛和掺杂硅层内的掺杂剂具有大于硅的原子尺寸的原子尺寸，因此松弛和掺杂硅层的面内晶格参数大于硅原子尺寸， 下层SOI层的平面晶格参数。 在SOI衬底上形成松弛和掺杂的硅层之后，从该层去除松弛和掺杂硅层内的掺杂剂，将松散和掺杂的硅层转化成形成在上层的应变（压缩或拉伸）硅层 SOI衬底的表面。

公开(公告)号：US08361889B2

公开(公告)日：2013-01-29

申请号：US12830626

申请日：2010-07-06

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L21/20

CPC分类号： H01L29/1054 ,  H01L29/7833

摘要： A method of forming a strained semiconductor-on-insulator (SSOI) substrate that does not include wafer bonding is provided. In this disclosure a relaxed and doped silicon layer is formed on an upper surface of a silicon-on-insulator (SOI) substrate. In one embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is smaller than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is smaller than the in-plane lattice parameter of the underlying SOI layer. In another embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is larger than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is larger than the in-plane lattice parameter of the underlying SOI layer. After forming the relaxed and doped silicon layer on the SOI substrate, the dopant within the relaxed and doped silicon layer is removed from that layer converting the relaxed and doped silicon layer into a strained (compressively or tensilely) silicon layer that is formed on an upper surface of an SOI substrate.

摘要翻译： 提供了一种形成不包括晶片接合的应变绝缘体上半导体（SSOI）衬底的方法。 在本公开中，在绝缘体上硅（SOI）衬底的上表面上形成松弛和掺杂的硅层。 在一个实施例中，松弛和掺杂硅层内的掺杂剂具有小于硅的原子尺寸的原子尺寸，因此松弛和掺杂硅层的面内晶格参数小于硅的原子尺寸， 下层SOI层的平面晶格参数。 在另一实施例中，松弛和掺杂硅层内的掺杂剂具有大于硅的原子尺寸的原子尺寸，因此松弛和掺杂硅层的面内晶格参数大于硅原子尺寸， 下层SOI层的平面晶格参数。 在SOI衬底上形成松弛和掺杂的硅层之后，从该层去除松弛和掺杂硅层内的掺杂剂，将松散和掺杂的硅层转化成形成在上层的应变（压缩或拉伸）硅层 SOI衬底的表面。