公开(公告)号：US20070058618A1

公开(公告)日：2007-03-15

申请号：US11288810

申请日：2005-11-28

申请人： Thungoc Tran ,  Sergey Shumarayev ,  Tim Hoang ,  Ning Xue ,  Chong Lee ,  Ramanand Venkata

发明人： Thungoc Tran ,  Sergey Shumarayev ,  Tim Hoang ,  Ning Xue ,  Chong Lee ,  Ramanand Venkata

IPC分类号： H04L12/50

CPC分类号： H03K19/17736 ,  H03K19/17744

摘要： An integrated circuit like a programmable logic device (“PLD”) includes multiple channels of data communication circuitry. Circuitry is provided for selectively sharing signals (e.g., control-type signals) among these channels in groupings of various size so that the device can better support communication protocols that require various numbers of channels (e.g., one channel operating relatively independently, four channels working together, eight channels working together, etc.). The signals shared may include a clock signal, a FIFO write enable signal, a FIFO read enable signal, or the like. The circuit arrangements are preferably modular (i.e., the same or substantially the same from one channel to the next and/or from one group of channels to the next) to facilitate such things as circuit design and verification.

摘要翻译： 诸如可编程逻辑器件（“PLD”）的集成电路包括多个通道的数据通信电路。 提供电路用于在各种尺寸的分组中选择性地共享这些信道中的信号（例如，控制型信号），使得设备可以更好地支持需要各种信道数量的通信协议（例如，一个信道相对独立地操作，四个信道工作 一起，八个渠道在一起等）。 共享的信号可以包括时钟信号，FIFO写使能信号，FIFO读使能信号等。 电路布置优选地是模块化的（即，从一个通道到下一个通道和/或从一组通道到下一个通道相同或基本相同），以促进诸如电路设计和验证的事情。

公开(公告)号：US20070043991A1

公开(公告)日：2007-02-22

申请号：US11359273

申请日：2006-02-21

申请人： Toan Nguyen ,  Thungoc Tran ,  Sergey Shumarayev ,  Arch Zaliznyak ,  Tim Hoang ,  Ramanand Venkata ,  Chong Lee

发明人： Toan Nguyen ,  Thungoc Tran ,  Sergey Shumarayev ,  Arch Zaliznyak ,  Tim Hoang ,  Ramanand Venkata ,  Chong Lee

IPC分类号： G01R31/28

CPC分类号： H03M9/00

摘要： Deserializer circuitry for high-speed serial data receiver circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry can also operate at any frequency in a wide range of frequencies. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

摘要翻译： 用于可编程逻辑器件（“PLD”）等上的高速串行数据接收器电路的解串器电路包括用于将串行数据转换成具有若干数据宽度的并行数据的电路。 电路也可以在宽频率范围内的任何频率下工作。 该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

公开(公告)号：US20070030184A1

公开(公告)日：2007-02-08

申请号：US11364589

申请日：2006-02-27

申请人： Toan Thanh Nguyen ,  Thungoc Tran ,  Sergey Shumarayev ,  Arch Zaliznyak ,  Shoujun Wang ,  Ramanand Venkata ,  Chong Lee

发明人： Toan Thanh Nguyen ,  Thungoc Tran ,  Sergey Shumarayev ,  Arch Zaliznyak ,  Shoujun Wang ,  Ramanand Venkata ,  Chong Lee

IPC分类号： H03M9/00

CPC分类号： H03K19/00 ,  H03K19/17744 ,  H03M9/00 ,  H04L1/243 ,  H04L7/0008 ,  H04L7/033 ,  H04L25/0266

摘要： Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

摘要翻译： 用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。 电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。 该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

公开(公告)号：US07697600B2

公开(公告)日：2010-04-13

申请号：US11182658

申请日：2005-07-14

申请人： Simardeep Maangat ,  Sergey Shumarayev ,  Wilson Wong ,  ThuNgoc Tran

发明人： Simardeep Maangat ,  Sergey Shumarayev ,  Wilson Wong ,  ThuNgoc Tran

IPC分类号： H03H7/30

CPC分类号： H04L25/03885 ,  H04B3/04 ,  H04L25/03019

摘要： Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry may be provided to compensate for attenuation caused by the transmission media. Equalization circuitry may include multiple stages arranged in series to allow the frequency responses of the stages to aggregate together. Each stage may be programmable to insert a zero, which causes the frequency response of the stage to increase in magnitude by 20 dB/decade. The frequency location of the zero may also be programmable to allow each stage to contribute a certain amount of gain for a specific frequency. Each stage may also be programmable to determine the location of poles for reduction of high frequency noise and cross-talk cancellation.

摘要翻译： 通过传输介质传输的数据信号遭受由传输介质引起的衰减。 可以提供均衡电路以补偿由传输介质引起的衰减。 均衡电路可以包括串联布置的多个级，以允许级的频率响应聚合在一起。 每个级可以是可编程的，以插入一个零，这使得该级的频率响应在幅度上增加20dB /十倍。 零的频率位置也可以是可编程的，以允许每个级对特定频率贡献一定量的增益。 每个阶段也可以被编程以确定用于降低高频噪声和串扰取消的极点的位置。

公开(公告)号：US20070014344A1

公开(公告)日：2007-01-18

申请号：US11182658

申请日：2005-07-14

申请人： Simardeep Maangat ,  Sergey Shumarayev ,  Wilson Wong ,  ThuNgoc Tran

发明人： Simardeep Maangat ,  Sergey Shumarayev ,  Wilson Wong ,  ThuNgoc Tran

IPC分类号： H03H7/30

CPC分类号： H04L25/03885 ,  H04B3/04 ,  H04L25/03019

摘要： Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry may be provided to compensate for attenuation caused by the transmission media. Equalization circuitry may include multiple stages arranged in series to allow the frequency responses of the stages to aggregate together. Each stage may be programmable to insert a zero, which causes the frequency response of the stage to increase in magnitude by 20 dB/decade. The frequency location of the zero may also be programmable to allow each stage to contribute a certain amount of gain for a specific frequency. Each stage may also be programmable to determine the location of poles for reduction of high frequency noise and cross-talk cancellation.

摘要翻译： 通过传输介质传输的数据信号遭受由传输介质引起的衰减。 可以提供均衡电路以补偿由传输介质引起的衰减。 均衡电路可以包括串联布置的多个级，以允许级的频率响应聚合在一起。 每个级可以是可编程的，以插入一个零，这使得该级的频率响应在幅度上增加20dB /十倍。 零的频率位置也可以是可编程的，以允许每个级对特定频率贡献一定量的增益。 每个阶段也可以被编程以确定用于降低高频噪声和串扰取消的极点的位置。

公开(公告)号：US07812659B1

公开(公告)日：2010-10-12

申请号：US11432420

申请日：2006-05-10

申请人： Sergey Shumarayev ,  Rakesh H Patel ,  William W Bereza ,  Tim Tri Hoang ,  Thungoc Tran

发明人： Sergey Shumarayev ,  Rakesh H Patel ,  William W Bereza ,  Tim Tri Hoang ,  Thungoc Tran

IPC分类号： G06F1/04 ,  H04L7/00

CPC分类号： H03L7/22 ,  G06F1/06

摘要： A programmable logic device (“PLD”) or the like has a plurality of data transmitter channels. Certain circuitry is shared by the channels. The shared circuitry includes at least one phase-locked loop (“PLL”) circuit for producing a primary clock signal, and global frequency divider circuitry for producing at least one global secondary clock signal based on the primary signal. The primary and global secondary signal(s) are distributed to the channels. Each of the channels includes local frequency divider circuitry for producing at least one local secondary clock signal based on the primary signal. Each channel also includes selection circuitry for selecting either the global or local secondary signal(s) for use by clock utilization circuitry of the channel. The clock utilization circuitry may include serializer circuitry for converting data from parallel to serial form.

摘要翻译： 可编程逻辑器件（“PLD”）等具有多个数据发送器通道。 某些电路由通道共享。 共享电路包括用于产生主时钟信号的至少一个锁相环（“PLL”）电路和用于基于主信号产生至少一个全局辅助时钟信号的全局分频器电路。 主要和全局辅助信号被分配到信道。 每个通道包括本地分频器电路，用于基于主信号产生至少一个本地辅助时钟信号。 每个通道还包括选择电路，用于选择由信道的时钟利用电路使用的全局或局部辅助信号。 时钟利用电路可以包括用于将数据从并行转换为串行形式的串行化器电路。

公开(公告)号：US08571059B1

公开(公告)日：2013-10-29

申请号：US13194536

申请日：2011-07-29

申请人： Arch Zaliznyak ,  Ramanand Venkata ,  Surinder Singh ,  Henry Y. Lui ,  Tim Tri Hoang ,  Sergey Shumarayev ,  Thungoc M. Tran

发明人： Arch Zaliznyak ,  Ramanand Venkata ,  Surinder Singh ,  Henry Y. Lui ,  Tim Tri Hoang ,  Sergey Shumarayev ,  Thungoc M. Tran

IPC分类号： H04J3/00

CPC分类号： G06F13/385

摘要： Disclosed are apparatus and methods for providing a serial interface with shared datapaths. The apparatus and methods share or re-use components from multiple lower-speed datapaths so as to efficiently provide a higher-speed datapath. In one embodiment, physical coding sublayer circuitry of the lower-speed datapaths is also used by the higher-speed datapath. In another embodiment, physical media access circuitry of the lower-speed data paths is also used by the higher-speed datapath. Other embodiments, aspects and features are also disclosed.

摘要翻译： 公开了用于提供具有共享数据路径的串行接口的装置和方法。 该装置和方法共享或重新使用来自多个低速数据路径的组件，以便有效地提供更高速度的数据通路。 在一个实施例中，低速数据路径的物理编码子层电路也被较高速数据路径使用。 在另一个实施例中，低速数据路径的物理介质访问电路也被高速数据路径使用。 还公开了其它实施例，方面和特征。

公开(公告)号：US20070041455A1

公开(公告)日：2007-02-22

申请号：US11361192

申请日：2006-02-23

申请人： Thungoc Tran ,  Sergey Shumarayev ,  Simardeep Maangat ,  Wilson Wong ,  Rakesh Patel

发明人： Thungoc Tran ,  Sergey Shumarayev ,  Simardeep Maangat ,  Wilson Wong ,  Rakesh Patel

IPC分类号： H04L25/00

CPC分类号： H04L1/243 ,  H04L25/03878

摘要： Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.

摘要翻译： 用于包含在PLD中的串行数据信号接收器电路包括串联连接并且可单独控制的多个均衡器电路，使得它们可以统一地补偿宽范围的可能的输入信号衰减特性。 其他电路特征可以相对于均衡器电路连接以给予接收机电路其他能力。 例如，这些其他特征可以包括各种类型的环回测试电路，可控终端电阻，可控共模电压以及用于检测输入信号的可控阈值。 接收器电路的控制的各个方面可以是可编程的。

公开(公告)号：US20070013411A1

公开(公告)日：2007-01-18

申请号：US11183288

申请日：2005-07-14

申请人： Kazi Asaduzzaman ,  Sergey Shumarayev ,  Thungoc Tran ,  Wilson Wong ,  Rakesh Patel

发明人： Kazi Asaduzzaman ,  Sergey Shumarayev ,  Thungoc Tran ,  Wilson Wong ,  Rakesh Patel

IPC分类号： H03K19/094

CPC分类号： H03K17/164

摘要： High speed transmitter drivers and other types of driver circuitry may be required to produce output signals with variable slew rates. Driver circuitry and methods for providing variable slew rate control are described. Pre-driver circuitry with variable slew-rate may be used to supply signals with variable slew rate at the driver input. The driver and/or pre-driver circuits may include transistors with variable drive strengths. The driver and/or pre-driver circuits may also include selectably enabled stages for varying the circuit drive strength. The pre-driver circuitry may be delay matched to maintain signal quality. Other circuitry and methods are also described.

摘要翻译： 可能需要高速变送器驱动器和其他类型的驱动电路来产生具有可变转换速率的输出信号。 描述了用于提供可变转换速率控制的驱动电路和方法。 可以使用具有可变转换速率的前驱动器电路在驱动器输入端提供具有可变转换速率的信号。 驱动器和/或预驱动器电路可以包括具有可变驱动强度的晶体管。 驱动器和/或预驱动器电路还可以包括用于改变电路驱动强度的可选择地启用的级。 预驱动器电路可以被延迟匹配以保持信号质量。 还描述了其它电路和方法。

公开(公告)号：US20070018863A1

公开(公告)日：2007-01-25

申请号：US11270718

申请日：2005-11-08

申请人： Tim Hoang ,  Sergey Shumarayev

发明人： Tim Hoang ,  Sergey Shumarayev

IPC分类号： H03M9/00

CPC分类号： G06F1/10 ,  H03K19/177 ,  H03K19/17736

摘要： Circuitry for distributing clock signals (e.g., reference clock signals) among a plurality of blocks of circuitry. Each block may include reference clock source circuitry and reference clock utilization circuitry. Each block also preferably includes an identical or substantially identical module of clock signal distribution circuitry that can (1) accept a signal from the source circuitry in that block, (2) apply any of several clock signals to the utilization circuitry in that block, and (3) connect to the similar module(s) of one or more adjacent blocks.

摘要翻译： 用于在多个电路块之间分配时钟信号（例如，参考时钟信号）的电路。 每个块可以包括参考时钟源电路和参考时钟利用电路。 每个块还优选地包括相同或基本相同的时钟信号分配电路模块，其可以（1）接收来自该块中的源电路的信号，（2）将几个时钟信号中的任何一个应用于该块中的利用电路，以及 （3）连接到一个或多个相邻块的相似模块。