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    Method for forming a deposited oxide layer
    3.
    发明授权
    Method for forming a deposited oxide layer 有权
    形成沉积氧化物层的方法

    公开(公告)号：US07767588B2

    公开(公告)日：2010-08-03

    申请号：US11364128

    申请日：2006-02-28

    Applicant: Tien Ying Luo ,  Rajesh A. Rao

    Inventor： Tien Ying Luo ,  Rajesh A. Rao

    IPC: H01L21/31 ,  H01L21/461

    CPC classification number: H01L21/28282 ,  B82Y10/00 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/31612 ,  H01L29/42332 ,  H01L29/7883 ,  H01L29/7885

    Abstract: An insulating layer formed by deposition is annealed in the presence of radical oxygen to reduce bond defects. A substrate is provided. An oxide layer is deposited overlying the substrate. The oxide layer has a plurality of bond defects. The oxide layer is annealed in the presence of radical oxygen to modify a substantial portion of the plurality of bond defects by using oxygen atoms. The anneal, in one form, is an in-situ steam generation (ISSG) anneal. In one form, the insulating layer overlies a layer of charge storage material, such as nanoclusters, that form a gate structure of a semiconductor storage device. The ISSG anneal repairs bond defects by oxidizing defective silicon bonds in the oxide layer when the oxide layer is silicon dioxide.

    Abstract translation: 通过沉积形成的绝缘层在自由基氧的存在下退火以减少键合缺陷。 提供基板。 沉积在衬底上的氧化物层。 氧化物层具有多个键合缺陷。 氧化层在自由基氧的存在下进行退火，通过使用氧原子来修饰多个键缺陷的大部分。 一种形式的退火是原位蒸汽发生（ISSG）退火。 在一种形式中，绝缘层覆盖形成半导体存储装置的栅极结构的诸如纳米团簇的电荷存储材料层。 当氧化物层是二氧化硅时，ISSG退火通过氧化氧化物层中的有缺陷的硅键来修复接合缺陷。

    Process of forming an electronic device including a control gate electrode, a semiconductor layer, and a select gate electrode
    6.
    发明授权
    Process of forming an electronic device including a control gate electrode, a semiconductor layer, and a select gate electrode 有权
    形成包括控制栅电极，半导体层和选择栅电极的电子器件的工艺

    公开(公告)号：US08803217B2

    公开(公告)日：2014-08-12

    申请号：US11685297

    申请日：2007-03-13

    Applicant: Rajesh A. Rao ,  Ramachandran Muralidhar

    Inventor： Rajesh A. Rao ,  Ramachandran Muralidhar

    IPC: H01L29/788

    CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

    Abstract: An electronic device including a nonvolatile memory cell can include a substrate including a first portion and a second portion, wherein a first major surface within the first portion lies at an elevation lower than a second major surface within the second portion. The electronic device can also include a charge storage stack overlying the first portion, wherein the charge storage stack includes discontinuous storage elements. The electronic device can further include a control gate electrode overlying the first portion, and a select gate electrode overlying the second portion, wherein the select gate electrode includes a sidewall spacer. In a particular embodiment, a process can be used to form the charge storage stack and control gate electrode. A semiconductor layer can be formed after the charge storage stack and control gate electrode are formed to achieve the substrate with different major surfaces at different elevations. The select gate electrode can be formed over the semiconductor layer.

    Abstract translation: 包括非易失性存储单元的电子设备可以包括包括第一部分和第二部分的基板，其中第一部分内的第一主表面位于比第二部分内的第二主表面低的高度处。 电子设备还可以包括覆盖第一部分的电荷存储堆叠，其中电荷存储堆叠包括不连续的存储元件。 电子器件还可以包括覆盖第一部分的控制栅电极和覆盖第二部分的选择栅电极，其中选择栅电极包括侧壁间隔物。 在特定实施例中，可以使用一种工艺来形成电荷存储堆和控制栅电极。 在形成电荷存储堆和控制栅电极之后可以形成半导体层，以在不同的高度实现具有不同主表面的衬底。 选择栅电极可以形成在半导体层上。

    Nanocrystal non-volatile memory cell and method therefor
    8.
    发明授权
    Nanocrystal non-volatile memory cell and method therefor 有权
    纳米晶体非挥发性记忆体及其方法

    公开(公告)号：US07800164B2

    公开(公告)日：2010-09-21

    申请号：US12397849

    申请日：2009-03-04

    Applicant: Ramachandran Muralidhar ,  Rajesh A. Rao ,  Michael A. Sadd ,  Bruce E. White

    Inventor： Ramachandran Muralidhar ,  Rajesh A. Rao ,  Michael A. Sadd ,  Bruce E. White

    IPC: H01L29/792

    CPC classification number: H01L29/42332 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/513 ,  H01L29/7881 ,  Y10S977/773

    Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.

    Abstract translation: 一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质 元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。 在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。

    Method for forming a split gate memory device
    9.
    发明授权
    Method for forming a split gate memory device 有权
    用于形成分离栅极存储器件的方法

    公开(公告)号：US07416945B1

    公开(公告)日：2008-08-26

    申请号：US11676403

    申请日：2007-02-19

    Applicant: Ramachandran Muralidhar ,  Rajesh A. Rao ,  Matthew T. Herrick ,  Narayanan C. Ramani ,  Robert F. Steimle

    Inventor： Ramachandran Muralidhar ,  Rajesh A. Rao ,  Matthew T. Herrick ,  Narayanan C. Ramani ,  Robert F. Steimle

    IPC: H01L21/336

    CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11521

    Abstract: A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial spacer. The sacrificial spacer is removed after the forming the layer of nanoclusters, wherein nanoclusters formed on the sacrificial spacer are removed and other nanoclusters remain. A layer of control gate material is formed over the substrate after the sacrificial spacer is removed. A control gate of a split gate memory device is formed from the layer of control gate material, wherein the control gate is located over remaining nanoclusters.

    Abstract translation: 一种方法形成分离栅极存储器件。 将衬底上的选择栅极材料层图案化以形成第一侧壁。 邻近第一侧壁形成牺牲隔离物。 纳米团簇形成在包括在牺牲间隔物上的衬底上。 在形成纳米团簇层之后去除牺牲隔离物，其中除去在牺牲隔离物上形成的纳米团簇并保留其他纳米团簇。 在除去牺牲间隔物之后，在衬底上形成一层控制栅极材料。 分离栅极存储器件的控制栅极由控制栅极材料层形成，其中控制栅极位于剩余的纳米簇上。

    METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING HIGH VOLTAGE TRANSISTORS, NON-VOLATILE MEMORY TRANSISTORS, AND LOGIC TRANSISTORS
    10.
    发明申请
    METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING HIGH VOLTAGE TRANSISTORS, NON-VOLATILE MEMORY TRANSISTORS, AND LOGIC TRANSISTORS 有权
    制造具有高电压晶体管的半导体器件，非易失性存储器晶体管和逻辑晶体管的方法

    公开(公告)号：US20080179658A1

    公开(公告)日：2008-07-31

    申请号：US11627725

    申请日：2007-01-26

    Applicant: Rajesh A. Rao ,  Ramachandran Muralidhar

    Inventor： Rajesh A. Rao ,  Ramachandran Muralidhar

    IPC: H01L29/792

    CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L21/823462 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/7887

    Abstract: A semiconductor device is made on a semiconductor substrate. A first insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a high voltage transistor in a first region of the semiconductor substrate. After the first insulating layer is formed, a second insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a non-volatile memory transistor in a second region of the substrate. After the second insulating layer is formed, a third insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a logic transistor in a third region of the substrate.

    Abstract translation: 在半导体衬底上制造半导体器件。 第一绝缘层形成在半导体衬底上，用作半导体衬底的第一区域中的高电压晶体管的栅极电介质。 在形成第一绝缘层之后，在半导体衬底上形成第二绝缘层，用作在衬底的第二区域中用作非易失性存储晶体管的栅极电介质。 在形成第二绝缘层之后，在半导体衬底上形成第三绝缘层，用作衬底的第三区域中用于逻辑晶体管的栅极电介质。

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