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    Method for forming a deposited oxide layer
    1.
    发明授权
    Method for forming a deposited oxide layer 有权
    形成沉积氧化物层的方法

    公开(公告)号：US07767588B2

    公开(公告)日：2010-08-03

    申请号：US11364128

    申请日：2006-02-28

    Applicant: Tien Ying Luo ,  Rajesh A. Rao

    Inventor： Tien Ying Luo ,  Rajesh A. Rao

    IPC: H01L21/31 ,  H01L21/461

    CPC classification number: H01L21/28282 ,  B82Y10/00 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/31612 ,  H01L29/42332 ,  H01L29/7883 ,  H01L29/7885

    Abstract: An insulating layer formed by deposition is annealed in the presence of radical oxygen to reduce bond defects. A substrate is provided. An oxide layer is deposited overlying the substrate. The oxide layer has a plurality of bond defects. The oxide layer is annealed in the presence of radical oxygen to modify a substantial portion of the plurality of bond defects by using oxygen atoms. The anneal, in one form, is an in-situ steam generation (ISSG) anneal. In one form, the insulating layer overlies a layer of charge storage material, such as nanoclusters, that form a gate structure of a semiconductor storage device. The ISSG anneal repairs bond defects by oxidizing defective silicon bonds in the oxide layer when the oxide layer is silicon dioxide.

    Abstract translation: 通过沉积形成的绝缘层在自由基氧的存在下退火以减少键合缺陷。 提供基板。 沉积在衬底上的氧化物层。 氧化物层具有多个键合缺陷。 氧化层在自由基氧的存在下进行退火，通过使用氧原子来修饰多个键缺陷的大部分。 一种形式的退火是原位蒸汽发生（ISSG）退火。 在一种形式中，绝缘层覆盖形成半导体存储装置的栅极结构的诸如纳米团簇的电荷存储材料层。 当氧化物层是二氧化硅时，ISSG退火通过氧化氧化物层中的有缺陷的硅键来修复接合缺陷。

    Multilayer silicon nitride deposition for a semiconductor device
    6.
    发明申请
    Multilayer silicon nitride deposition for a semiconductor device 审中-公开
    用于半导体器件的多层氮化硅沉积

    公开(公告)号：US20080173908A1

    公开(公告)日：2008-07-24

    申请号：US11655461

    申请日：2007-01-19

    Applicant: Kurt H. Junker ,  Paul A. Grudowski ,  Xiang-Zheng Bo ,  Tien Ying Luo

    Inventor： Kurt H. Junker ,  Paul A. Grudowski ,  Xiang-Zheng Bo ,  Tien Ying Luo

    IPC: H01L29/78 ,  H01L21/3105 ,  H01L21/8238

    CPC classification number: H01L21/02348 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02351 ,  H01L21/3105 ,  H01L21/3185 ,  H01L21/823807 ,  H01L29/7843

    Abstract: A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (131) of a first stressor material over the semiconductor structure, said first stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (133) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.

    Abstract translation: 提供了制造半导体器件的方法，其包括（a）提供配备有栅极和沟道区域的半导体结构，所述沟道区域与栅极相关联; （b）在半导体结构上沉积第一应力源材料的第一子层（131），所述第一应力源材料含有硅 - 氮键并向半导体结构施加拉伸应力; （c）通过暴露于辐射源固化第一应激物材料; （d）在所述第一子层上沉积第二应力源材料的第二子层（133），所述第二应力源材料含有硅 - 氮键并向所述半导体结构施加拉伸应力; 和（e）通过暴露于辐射源固化应力源材料的第二子层。

    Dual high-K oxides with SiGe channel
    7.
    再颁专利
    Dual high-K oxides with SiGe channel 有权
    具有SiGe通道的双高K氧化物

    公开(公告)号：USRE45955E1

    公开(公告)日：2016-03-29

    申请号：US14452736

    申请日：2014-08-06

    Applicant: Tien Ying Luo ,  Gauri V. Karve ,  Daniel K. Tekleab

    Inventor： Tien Ying Luo ,  Gauri V. Karve ,  Daniel K. Tekleab

    IPC: H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49

    CPC classification number: H01L21/823857 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

    Abstract: A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices (50, 52) and core transistor devices (51, 53) on a single substrate (15) having a silicon germanium channel layer (21) in the PMOS device areas (112, 113), where each DGO transistor device (50, 52) includes a metal gate (25), an upper gate oxide region (60, 84) formed from a second, relatively higher high-k metal oxide layer (24), and a lower gate oxide region (58, 84) formed from a first relatively lower high-k layer (22), and where each core transistor device (51, 53) includes a metal gate (25) and a core gate dielectric layer (72, 98) formed from only the second, relatively higher high-k metal oxide layer (24).

    Abstract translation: 描述了用于在PMOS器件中具有硅锗沟道层（21）的单个衬底（15）上集成双栅极氧化物（DGO）晶体管器件（50,52）和核心晶体管器件（51,53）的方法和装置 区域（112,113），其中每个DGO晶体管器件（50,52）包括金属栅极（25），由第二相对较高的高k金属氧化物层（24）形成的上部栅极氧化区域（60,84） ）和由第一相对较低的高k层（22）形成的下栅极氧化物区域（58,84），并且其中每个核心晶体管器件（51,53）包括金属栅极（25）和芯栅极电介质 仅由第二相对较高的高k金属氧化物层（24）形成的层（72,98）。

    MULTILAYER SILICON NITRIDE DEPOSITION FOR A SEMICONDUCTOR DEVICE
    9.
    发明申请
    MULTILAYER SILICON NITRIDE DEPOSITION FOR A SEMICONDUCTOR DEVICE 审中-公开
    用于半导体器件的多层硅氮化物沉积

    公开(公告)号：US20110210401A1

    公开(公告)日：2011-09-01

    申请号：US12713262

    申请日：2010-02-26

    Applicant: Kurt H. Junker ,  Paul A. Grudowski ,  Xiang-Zheng Bo ,  Tien Ying Luo

    Inventor： Kurt H. Junker ,  Paul A. Grudowski ,  Xiang-Zheng Bo ,  Tien Ying Luo

    IPC: H01L27/092 ,  H01L29/78

    CPC classification number: H01L21/823807 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02274 ,  H01L27/092 ,  H01L29/78 ,  H01L29/7843

    Abstract: A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate (209) and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (231) of a first stressor material over the semiconductor structure, said first stressor material containing silicon- nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (233) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.

    Abstract translation: 提供一种制造半导体器件的方法，其包括（a）提供配备有栅极（209）和沟道区域的半导体结构，所述沟道区域与栅极相关联; （b）在半导体结构上沉积第一应力源材料的第一子层（231），所述第一应力材料含有硅 - 氮键并向半导体结构施加拉伸应力; （c）通过暴露于辐射源固化第一应激物材料; （d）在所述第一子层上沉积第二应力源材料的第二子层（233），所述第二应力材料含有硅 - 氮键并向所述半导体结构施加拉伸应力; 和（e）通过暴露于辐射源固化应力源材料的第二子层。

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