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公开(公告)号：US07707535B2
公开(公告)日：2010-04-27
申请号：US11849461
申请日：2007-09-04
申请人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
发明人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
IPC分类号： G06F17/50
CPC分类号： G03F7/70475 , G03F7/70466 , G03F7/70691
摘要： Stitched integrated circuit (IC) chip layout design structures are disclosed. In one embodiment, a design structure embodied in a machine readable medium used in a design process includes: an integrated circuit (IC) chip layout exceeding a size of a photolithography tool field, the IC chip layout including: a plurality of stitched regions including at least one redundant stitched region or at least one unique stitched region; and for each stitched region: a boundary identification identifying a boundary of the stitched region at which stitching occurs.
摘要翻译： 公开了拼接集成电路（IC）芯片布局设计结构。 在一个实施例中，在设计过程中使用的机器可读介质中体现的设计结构包括：超过光刻工具领域尺寸的集成电路（IC）芯片布局，所述IC芯片布局包括：多个缝合区域， 至少一个冗余缝合区域或至少一个独特的缝合区域; 并且针对每个缝合区域：识别发生缝合的缝合区域的边界的边界标识。
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公开(公告)号：US20080209382A1
公开(公告)日：2008-08-28
申请号：US11849461
申请日：2007-09-04
申请人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
发明人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
IPC分类号： G06F17/50
CPC分类号： G03F7/70475 , G03F7/70466 , G03F7/70691
摘要： Stitched integrated circuit (IC) chip layout design structures are disclosed. In one embodiment, a design structure embodied in a machine readable medium used in a design process includes: an integrated circuit (IC) chip exceeding a size of a photolithography tool field, the IC chip layout including: a plurality of stitched regions including at least one redundant stitched region or at least one unique stitched region; and for each stitched region: a boundary identification identifying a boundary of the stitched region at which stitching occurs.
摘要翻译： 公开了拼接集成电路（IC）芯片布局设计结构。 在一个实施例中，体现在设计过程中使用的机器可读介质中的设计结构包括：超过光刻工具领域尺寸的集成电路（IC）芯片，所述IC芯片布局包括：至少包括多个缝合区域 一个冗余缝合区域或至少一个独特的缝合区域; 并且针对每个缝合区域：识别发生缝合的缝合区域的边界的边界标识。
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公开(公告)号：US20080208383A1
公开(公告)日：2008-08-28
申请号：US11678069
申请日：2007-02-23
申请人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
发明人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
IPC分类号： G06F19/00
CPC分类号： G03F7/70475 , G03F7/70466 , G03F7/70691
摘要： Stitched integrated circuit (IC) chip layout methods, systems and program products are disclosed. In one embodiment, a method includes obtaining from a first entity a circuit design for an IC chip layout that exceeds a size of a photolithography tool field at a second entity, wherein the IC chip layout includes for at least one stitched region of a plurality of stitched regions: a boundary identification identifying a boundary of the at least one stitched region at which stitching occurs and a type indicator indicating whether the at least one stitched region is one of: redundant and unique; dissecting the IC chip layout into stitched regions indicated as unique or redundant at the second entity; and generating a photolithographic reticle at the second entity based on the plurality of stitched regions, the photolithographic reticle having a size that fits within the size of the photolithographic tool field at the second entity.
摘要翻译： 公布了拼接集成电路（IC）芯片布局方法，系统和程序产品。 在一个实施例中，一种方法包括从第一实体获得超过第二实体上的光刻工具区域的尺寸的IC芯片布局的电路设计，其中IC芯片布局包括用于多个 缝合区域：识别发生缝合的至少一个缝合区域的边界的边界标识和指示所述至少一个缝合区域是否是以下之一的类型指示器：冗余且唯一; 将IC芯片布局解剖为在第二实体处表示为唯一或冗余的缝合区域; 以及基于所述多个缝合区域在所述第二实体处产生光刻掩模版，所述光刻掩模版具有适合在所述第二实体处的所述光刻工具区域的尺寸内的尺寸。
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公开(公告)号：US07703060B2
公开(公告)日：2010-04-20
申请号：US11678069
申请日：2007-02-23
申请人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
发明人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
IPC分类号： G06F17/50
CPC分类号： G03F7/70475 , G03F7/70466 , G03F7/70691
摘要： Stitched integrated circuit (IC) chip layout methods, systems and program products are disclosed. In one embodiment, a method includes obtaining from a first entity a circuit design for an IC chip layout that exceeds a size of a photolithography tool field at a second entity, wherein the IC chip layout includes for at least one stitched region of a plurality of stitched regions: a boundary identification identifying a boundary of the at least one stitched region at which stitching occurs and a type indicator indicating whether the at least one stitched region is one of: redundant and unique; dissecting the IC chip layout into stitched regions indicated as unique or redundant at the second entity; and generating a photolithographic reticle at the second entity based on the plurality of stitched regions, the photolithographic reticle having a size that fits within the size of the photolithographic tool field at the second entity.
摘要翻译： 公布了拼接集成电路（IC）芯片布局方法，系统和程序产品。 在一个实施例中，一种方法包括从第一实体获得超过第二实体上的光刻工具区域的尺寸的IC芯片布局的电路设计，其中IC芯片布局包括用于多个 缝合区域：识别发生缝合的至少一个缝合区域的边界的边界标识和指示所述至少一个缝合区域是否是以下之一的类型指示器：冗余且唯一; 将IC芯片布局解剖为在第二实体处表示为唯一或冗余的缝合区域; 以及基于所述多个缝合区域在所述第二实体处产生光刻掩模版，所述光刻掩模版具有适合在所述第二实体处的所述光刻工具区域的尺寸内的尺寸。
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公开(公告)号：US07876952B2
公开(公告)日：2011-01-25
申请号：US12175576
申请日：2008-07-18
IPC分类号： G06K9/00
CPC分类号： G06F17/5068 , G03F1/68
摘要： A method for reducing a number of shapes, and a computer readable program code adapted to perform said method. The method forms first and second shape patterns. The second shape pattern includes the first shape pattern and error shapes. The error shapes are extracted from the second shape pattern. At least one environment shape corresponding to each error shape is derived from a subset of the error shapes. For example, each error shape in the subset may be expanded to form a corresponding expanded shape, and at least one environment shape corresponding to each expanded shape may be formed by removing all portions of the expanded shape common to the second shape pattern. The environment shape reflects a local geometric environment of its corresponding error shape. A subset of the environment shapes are deleted such that only unique environment shapes satisfying a selection criterion remain.
摘要翻译： 一种用于减少形状的方法，以及适于执行所述方法的计算机可读程序代码。 该方法形成第一和第二形状图案。 第二形状图案包括第一形状图案和错误形状。 从第二形状图案提取错误形状。 从错误形状的子集中导出与每个错误形状对应的至少一个环境形状。 例如，子集中的每个错误形状可以被扩展以形成对应的扩展形状，并且可以通过去除与第二形状图案相同的扩展形状的所有部分来形成与每个扩展形状对应的至少一个环境形状。 环境形状反映了其相应错误形状的局部几何环境。 环境形状的一个子集被删除，使得仅保持满足选择标准的独特环境形状。
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公开(公告)号：US07542599B2
公开(公告)日：2009-06-02
申请号：US11776769
申请日：2007-07-12
IPC分类号： G06K9/00
CPC分类号： G06F17/5068 , G03F1/68
摘要： A method for reducing a number of shapes, and a computer readable program code adapted to perform said method. The method forms first and second shape patterns. The second shape pattern includes the first shape pattern and error shapes. The error shapes are extracted from the second shape pattern. At least one environment shape corresponding to each error shape is derived from a subset of the error shapes. For example, each error shape in the subset may be expanded to form a corresponding expanded shape, and at least one environment shape corresponding to each expanded shape may be formed by removing all portions of the expanded shape common to the second shape pattern. The environment shape reflects a local geometric environment of its corresponding error shape. A subset of the environment shapes are deleted such that only unique environment shapes satisfying a selection criterion remain.
摘要翻译： 一种用于减少形状的方法，以及适于执行所述方法的计算机可读程序代码。 该方法形成第一和第二形状图案。 第二形状图案包括第一形状图案和错误形状。 从第二形状图案提取错误形状。 从错误形状的子集中导出与每个错误形状对应的至少一个环境形状。 例如，子集中的每个错误形状可以被扩展以形成对应的扩展形状，并且可以通过去除与第二形状图案相同的扩展形状的所有部分来形成与每个扩展形状对应的至少一个环境形状。 环境形状反映了其相应错误形状的局部几何环境。 环境形状的一个子集被删除，使得仅保持满足选择标准的独特环境形状。
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公开(公告)号：US20090016596A1
公开(公告)日：2009-01-15
申请号：US12175576
申请日：2008-07-18
IPC分类号： G06K9/00
CPC分类号： G06F17/5068 , G03F1/68
摘要： A method for reducing a number of shapes, and a computer readable program code adapted to perform said method. The method forms first and second shape patterns. The second shape pattern includes the first shape pattern and error shapes. The error shapes are extracted from the second shape pattern. At least one environment shape corresponding to each error shape is derived from a subset of the error shapes. For example, each error shape in the subset may be expanded to form a corresponding expanded shape, and at least one environment shape corresponding to each expanded shape may be formed by removing all portions of the expanded shape common to the second shape pattern. The environment shape reflects a local geometric environment of its corresponding error shape. A subset of the environment shapes are deleted such that only unique environment shapes satisfying a selection criterion remain.
摘要翻译： 一种用于减少形状的方法，以及适于执行所述方法的计算机可读程序代码。 该方法形成第一和第二形状图案。 第二形状图案包括第一形状图案和错误形状。 从第二形状图案提取错误形状。 从错误形状的子集中导出与每个错误形状对应的至少一个环境形状。 例如，子集中的每个错误形状可以被扩展以形成对应的扩展形状，并且可以通过去除与第二形状图案相同的扩展形状的所有部分来形成与每个扩展形状对应的至少一个环境形状。 环境形状反映了其相应错误形状的局部几何环境。 环境形状的一个子集被删除，使得仅保持满足选择标准的独特环境形状。
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公开(公告)号：US07289658B2
公开(公告)日：2007-10-30
申请号：US10604063
申请日：2003-06-24
IPC分类号： G06K9/00
CPC分类号： G06F17/5068 , G03F1/68
摘要： A method for reducing a number of shapes, and a computer readable program code adapted to perform said method. The method forms first and second shape patterns. The second shape pattern includes the first shape pattern and error shapes. The error shapes are extracted from the second shape pattern. At least one environment shape corresponding to each error shape is derived from a subset of the error shapes. For example, each error shape in the subset may be expanded to form a corresponding expanded shape, and at least one environment shape corresponding to each expanded shape may be formed by removing all portions of the expanded shape common to the second shape pattern. The environment shape reflects a local geometric environment of its corresponding error shape. A subset of the environment shapes are deleted such that only unique environment shapes satisfying a selection criterion remain.
摘要翻译： 一种用于减少形状的方法，以及适于执行所述方法的计算机可读程序代码。 该方法形成第一和第二形状图案。 第二形状图案包括第一形状图案和错误形状。 从第二形状图案提取错误形状。 从错误形状的子集中导出与每个错误形状对应的至少一个环境形状。 例如，子集中的每个错误形状可以被扩展以形成对应的扩展形状，并且可以通过去除与第二形状图案相同的扩展形状的所有部分来形成与每个扩展形状对应的至少一个环境形状。 环境形状反映了其相应错误形状的局部几何环境。 环境形状的一个子集被删除，使得仅保持满足选择标准的独特环境形状。
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公开(公告)号：US07685544B2
公开(公告)日：2010-03-23
申请号：US11947254
申请日：2007-11-29
申请人： David L. DeMaris , Timothy G. Dunham , William C. Leipold , Daniel N. Maynard , Michael E. Scaman , Shi Zhong
发明人： David L. DeMaris , Timothy G. Dunham , William C. Leipold , Daniel N. Maynard , Michael E. Scaman , Shi Zhong
IPC分类号： G06F17/50
摘要： A computer program product for generating test patterns for a pattern sensitive algorithm. The program product includes code for extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
摘要翻译： 一种用于生成模式敏感算法的测试模式的计算机程序产品。 程序产品包括从布局设计中提取特征样本的代码; 将特征样本分组成簇; 从布局设计中选择至少一个覆盖每个聚类的特征样本的区域; 并且将至少一个区域覆盖的每个模式布局保存为测试模式。
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10.发明授权Methodology to improve turnaround for integrated circuit design using geometrical hierarchy 失效使用几何层次结构改善集成电路设计周转的方法公开(公告)号：US07669175B2
公开(公告)日：2010-02-23
申请号：US11747485
申请日：2007-05-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method of designing a layout for manufacturing an integrated circuit is provided, in which computationally intensive portions of the design process, such as simulation of an image transferred through a mask design, or simulation of electrical characteristics of a circuit, are performed more efficiently by only performing such computations on single instance of computational subunits that have an identical geometrical context. Thus, rather than performing such computations based on the functional layout, for which typical design process steps result in significant flattening of the functional hierarchy, and therefore increase the cost of computation, the invention performs simulations on computational subunits stored in a hierarchy based on geometrical context, which minimizes the cost of simulation. The resulting simulation results are subsequently assembled according to the functional layout.
摘要翻译： 提供了一种设计用于制造集成电路的布局的方法，其中，通过设计处理的计算密集部分（诸如通过掩模设计传送的图像的模拟）或电路的电特性的模拟被更高效地执行 仅在具有相同几何上下文的计算子单元的单个实例上执行这样的计算。 因此，不是基于功能布局执行这样的计算，而是通过典型的设计过程步骤导致功能层次结构的显着平坦化，从而增加计算成本，本发明对基于几何的层次结构存储的计算子单元进行模拟 上下文，最大限度地降低了模拟成本。 随后根据功能布局组合得到的模拟结果。
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