公开(公告)号：US5210828A

公开(公告)日：1993-05-11

申请号：US504764

申请日：1990-04-04

申请人： Timothy V. Bolan ,  Josephine A. Boston ,  George A. Fax ,  Donald J. Hanrahan ,  Bernhard Laubli ,  David A. Ring ,  Alfred T. Rundle ,  David J. Shippy

发明人： Timothy V. Bolan ,  Josephine A. Boston ,  George A. Fax ,  Donald J. Hanrahan ,  Bernhard Laubli ,  David A. Ring ,  Alfred T. Rundle ,  David J. Shippy

IPC分类号： G06F15/167

CPC分类号： G06F15/167

摘要： A plurality of processors are connected to the interprocessor communications facility in the multiprocessing system of the invention. The interprocessor communications facility has arbitration circuitry, mailbox circuitry, and processor interrupt circuitry. The interprocessor communications facility of the invention is centralized and does not require the use of main storage. This enables processors to communicate with each other in a fast and efficient manner. The arbitration circuitry prevents simultaneous access of the interprocessor communications facility by more than one processor, and decodes the commands sent from the processors and routes them to the processor interrupt circuitry or to the mailbox circuitry, depending on the command. The mailbox circuitry of the invention receives messages from sending processors and provides them to the intended receiving processors in a safe and secure manner. The processor interrupt circuitry facilitates the interprocessor communications process by handling interprocessor interrupts.

摘要翻译： 多个处理器连接到本发明的多处理系统中的处理器间通信设施。 处理器间通信设施具有仲裁电路，邮箱电路和处理器中断电路。 本发明的处理器间通信设施是集中式的，不需要使用主存储器。 这使得处理器能够以快速和有效的方式相互通信。 仲裁电路防止多个处理器同时访问处理器间通信设施，并根据命令解码从处理器发送的命令并将它们路由到处理器中断电路或邮箱电路。 本发明的邮箱电路从发送处理器接收消息，并以安全和可靠的方式将它们提供给预期的接收处理器。 处理器中断电路通过处理处理器间中断来促进处理器之间的通信过程。

公开(公告)号：US06219813B1

公开(公告)日：2001-04-17

申请号：US09106959

申请日：1998-06-29

申请人： James W. Bishop ,  George A. Fax ,  Robert G. Iseminger

发明人： James W. Bishop ,  George A. Fax ,  Robert G. Iseminger

IPC分类号： G06F1100

CPC分类号： G01R31/31937 ,  G01R31/3016 ,  G06F1/025

摘要： A programmable timing circuit on an integrated circuit chip for testing the cycle time of functional circuits on the chip. The timing circuit includes a selectable input having at least two sources, one of which is a toggle circuit; a minimally delayed control path including a control latch; a programmable delay path in parallel with the control path and including a sample latch; and a comparator for comparing the state of the control latch and sample latches to provide a signal indicative of the delay path being longer than the control path. A plurality of configuration latches and multiplexers are provided for selecting the input source and routing an input signal through specific delay blocks to control the amount of delay in the delay path.

公开(公告)号：US06415402B2

公开(公告)日：2002-07-02

申请号：US09768637

申请日：2001-01-24

申请人： James W. Bishop ,  George A. Fax ,  Robert G. Iseminger

发明人： James W. Bishop ,  George A. Fax ,  Robert G. Iseminger

IPC分类号： G01R3128

CPC分类号： G01R31/31937 ,  G01R31/3016 ,  G06F1/025

摘要： A programmable timing circuit on an integrated circuit chip for testing the cycle time of functional circuits on the chip. The timing circuit includes a selectable input having at least two sources, one of which is a toggle circuit; a minimally delayed control path including a control latch; a programmable delay path in parallel with the control path and including a sample latch; and a comparator for comparing the state of the control latch and sample latches to provide a signal indicative of the delay path being longer than the control path. A plurality of configuration latches and multiplexers are provided for selecting the input source and routing an input signal through specific delay blocks to control the amount of delay in the delay path.

摘要翻译： 集成电路芯片上的可编程定时电路，用于测试芯片上功能电路的周期时间。 定时电路包括具有至少两个源的可选择输入，其中之一是触发电路; 包括控制锁存器的最小延迟控制路径; 与所述控制路径并联并包括样本锁存器的可编程延迟路径; 以及用于比较控制锁存器和采样锁存器的状态以提供指示延迟路径比控制路径长的信号的比较器。 提供多个配置锁存器和多路复用器用于选择输入源并通过特定延迟块路由输入信号以控制延迟路径中的延迟量。