公开(公告)号：US07863941B1

公开(公告)日：2011-01-04

申请号：US12365585

申请日：2009-02-04

申请人： Toan Thanh Nguyen ,  Thungoc M. Tran ,  Sergey Shumarayev

发明人： Toan Thanh Nguyen ,  Thungoc M. Tran ,  Sergey Shumarayev

IPC分类号： H03K5/22

CPC分类号： H03K3/356139 ,  G11C7/065

摘要： A circuit includes a differential circuit that generates a differential output signal at first and second output nodes. The circuit also includes a first variable capacitor coupled to the first output node of the differential circuit, and a second variable capacitor coupled to the second output node of the differential circuit. A control circuit controls capacitances of the first and the second variable capacitors in response to a measurement of the differential output signal.

摘要翻译： 电路包括在第一和第二输出节点处产生差分输出信号的差分电路。 电路还包括耦合到差分电路的第一输出节点的第一可变电容器和耦合到差分电路的第二输出节点的第二可变电容器。 响应于差分输出信号的测量，控制电路控制第一和第二可变电容器的电容。

公开(公告)号：US08464088B1

公开(公告)日：2013-06-11

申请号：US12915794

申请日：2010-10-29

申请人： Toan Thanh Nguyen ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Weiqi Ding ,  Thungoc M. Tran

发明人： Toan Thanh Nguyen ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Weiqi Ding ,  Thungoc M. Tran

IPC分类号： G06F1/04

CPC分类号： G06F1/04 ,  G06F1/10

摘要： Various methods and structures related to clock distribution for flexible channel bonding are disclosed. One embodiment provides a clock network in physical media attachment (“PMA”) circuitry, a specific type or portion of system interconnect circuitry, arranged in pairs of channel groups. In one embodiment, clock generation circuitry blocks (“CGBs”) in each pair of channel groups receives outputs of multiple phased locked loop circuits (“PLLs”) which can be selectively utilized by the CGBs to generate PMA clock signals. In another embodiment, the CGBs can also select output of a clock data recovery (“CDR”)/transmit PLL circuitry block in one of the channels of a channel group of the pair of channel groups. In one embodiment, first groups of connection lines couple circuitry in a channel group pair such that a designated CGB in each channel group pair can provide clock signals to one or more of the channels in the channel group pair. In one embodiment, second groups of connection lines connect channels in one channel group pair to channels in other channel group pairs such that one or more channels across the channel group pairs can receive a clock signal generated by a CGB in a designated channel. These and other embodiments are described more fully in the disclosure.

摘要翻译： 公开了与用于柔性通道结合的时钟分配有关的各种方法和结构。 一个实施例提供物理介质连接（“PMA”）电路中的时钟网络，系统互连电路的特定类型或部分，被布置成成对的信道组。 在一个实施例中，每对信道组中的时钟产生电路块（“CGB”）接收多个锁相环电路（“PLL”）的输出，这些电路可被CGB选择性地用于产生PMA时钟信号。 在另一个实施例中，CGB还可以在一对信道组的信道组的信道之一中选择时钟数据恢复（“CDR”）/发送PLL电路块的输出。 在一个实施例中，第一组连接线将信道组对中的电路耦合，使得每个信道组对中的指定CGB可以向信道组对中的一个或多个信道提供时钟信号。 在一个实施例中，第二组连接线将一个信道组对中的信道与其它信道组对中的信道相连，使得跨信道组对的一个或多个信道可以接收由指定信道中的CGB产生的时钟信号。 在本公开中更全面地描述了这些和其它实施例。

公开(公告)号：US07245240B1

公开(公告)日：2007-07-17

申请号：US11370727

申请日：2006-03-07

申请人： Toan Thanh Nguyen ,  Thungoc M. Tran ,  Sergey Shumarayev

发明人： Toan Thanh Nguyen ,  Thungoc M. Tran ,  Sergey Shumarayev

IPC分类号： H03M9/00

CPC分类号： H03M9/00 ,  H03K5/135 ,  H03K5/15013

摘要： Integrated circuit serializer circuitry is provided that converts parallel data to serial data on an integrated circuit. A two-phase global serializer master clock generator uses a four-phase internal clock to generate a two-phase global serializer master clock. The two-phase global serializer master clock is distributed globally on the integrated circuit using a distribution path. The integrated circuit has multiple serial communications channels each of which has an associated serializer. Each serializer contains circuitry that derives a number of clock signals from the two phases of the global serializer master clock. Each serializer uses the derived clocks in converting parallel data to serial data for transmission over its associated serial communications channel. The serializers each contain two smaller serializers that convert first and second sets of parallel data to first and second serial outputs. A 2:1 serializer in each serializer merges the first and second serial outputs.

摘要翻译： 提供集成电路串行化器电路，其将并行数据转换为集成电路上的串行数据。 两相全局串行器主时钟发生器使用四相内部时钟来生成两相全局串行器主时钟。 两相全局串行器主时钟使用分布路径全局分布在集成电路上。 集成电路具有多个串行通信通道，每个通道具有相关联的串行器。 每个串行器包含从全局串行器主时钟的两个相位导出多个时钟信号的电路。 每个串行器使用派生时钟将并行数据转换为串行数据，以便通过其相关联的串行通信通道进行传输。 串行器每个都包含两个较小的串行器，它们将第一和第二组并行数据转换为第一和第二串行输出。 每个串行器中的2：1串行器合并第一个和第二个串行输出。

公开(公告)号：US07482841B1

公开(公告)日：2009-01-27

申请号：US11731463

申请日：2007-03-29

申请人： Toan Thanh Nguyen ,  Thungoc M. Tran

发明人： Toan Thanh Nguyen ,  Thungoc M. Tran

IPC分类号： H03D13/00

CPC分类号： H03D13/004

摘要： Bang-bang phase detection (BBPD) methods and circuits are presented for providing low latency, low jitter phase detection for use in high data-rate applications. A shortened data-path implementation of BBPD methods and circuits provides low-latency production of two output signals including alternating samples of the input signal. Combinational logic circuitry is also provided to produce a clock-data recovery (CDR) signal indicative of the phase of the input signal with respect to a clock signal. The use of differential signals throughout the BBPD timing circuitry provides for the production of a low jitter CDR signal.

摘要翻译： 提出了Bang-bang相位检测（BBPD）方法和电路，用于提供低延迟，低抖动相位检测，用于高数据速率应用。 BBPD方法和电路的缩短的数据路径实现提供了低延迟生成两个输出信号，包括输入信号的交替采样。 还提供组合逻辑电路以产生指示相对于时钟信号的输入信号的相位的时钟数据恢复（CDR）信号。 在整个BBPD定时电路中使用差分信号提供低抖动CDR信号的产生。

公开(公告)号：US07777529B1

公开(公告)日：2010-08-17

申请号：US11269456

申请日：2005-11-07

申请人： Toan Thanh Nguyen ,  Thungoc M. Tran

发明人： Toan Thanh Nguyen ,  Thungoc M. Tran

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/412 ,  H03K19/0008

摘要： A dynamic flip-flop includes a leakage compensation circuit enabling operation over a wide range of frequencies. Nodes of the dynamic flip-flop store the flip-flop's state. The leakage compensation circuit drains leakage currents from these nodes to prevent the node voltage from rising and triggering an erroneous state change when a data signal changes in the middle of the clock cycle. The leakage compensation circuit associated with a node is activated when the node is set to a low logic level voltage. The leakage compensation circuit is adapted to draw a current from a node that compensates for the leakage current supplied to the node. At the least, this current draw is sufficient to prevent the voltage at the node from rising above a state change threshold voltage during the time period between refresh operations.

摘要翻译： 动态触发器包括允许在宽范围的频率上操作的漏电补偿电路。 动态触发器的节点存储触发器的状态。 当数据信号在时钟周期的中间改变时，泄漏补偿电路从这些节点漏出漏电流，以防止节点电压上升并触发错误状态改变。 当节点设置为低逻辑电平电压时，与节点相关联的漏电补偿电路被激活。 泄漏补偿电路适于从节点抽取电流来补偿提供给节点的漏电流。 至少，这种电流消耗足以防止在刷新操作期间节点处的电压升高到高于状态变化阈值电压。

公开(公告)号：US08626474B2

公开(公告)日：2014-01-07

申请号：US12762848

申请日：2010-04-19

申请人： Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

发明人： Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

IPC分类号： G06F7/60 ,  G06G7/62 ,  G06F17/50

CPC分类号： G06F17/5009 ,  G06F17/5036 ,  G06F2217/10

摘要： A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.

摘要翻译： 提供了一种用于模拟高速通信链路系统的链路仿真工具。 通信链路可以包括链路子系统，例如发射（TX）电路，接收（TX）电路，向TX和RX电路提供参考时钟信号的振荡器电路，以及链接TX和RX电路的信道。 链接仿真工具可以使用行为模型对每个子系统进行建模。 行为模型可以包括特征功能，例如传递函数，概率密度函数和眼睛特征。 链路仿真工具可以具有能够执行二维（双变量）卷积运算并且对由行为模型提供的特征函数应用双域（频率 - 时间）变换以模拟性能的链路分析引擎 的链接系统。 链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。

公开(公告)号：US08290750B1

公开(公告)日：2012-10-16

申请号：US13036437

申请日：2011-02-28

申请人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

发明人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

IPC分类号： H03F1/26

CPC分类号： H03K5/19 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/1778

摘要： Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.

摘要翻译： 串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。 可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。 用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。 因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。 可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。 该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。

公开(公告)号：US07860203B1

公开(公告)日：2010-12-28

申请号：US11725653

申请日：2007-03-19

申请人： Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran

发明人： Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran

IPC分类号： H04L7/00

CPC分类号： H03L7/087 ,  H04J3/0688 ,  H04L7/033

摘要： A programmable logic device integrated circuit (“PLD”) includes high-speed serial interface (“HSSI”) circuitry in addition to programmable logic circuitry. The HSSI circuitry includes multiple channels of nominal data-handling circuitry (typically including clock and data recovery (“CDR”) circuitry), and at least one channel of nominal clock management unit (“CMU”) circuitry (typically including phase-locked loop (“PLL”) circuitry or the like). To increase the flexibility with which the channels can be used, the nominal data-handling channels are equipped to alternatively perform CMU-type functions, and the nominal CMU channel is equipped to alternatively perform data-handling functions.

摘要翻译： 可编程逻辑器件集成电路（“PLD”）除了可编程逻辑电路之外还包括高速串行接口（“HSSI”）电路。 HSSI电路包括多个标称数据处理电路（通常包括时钟和数据恢复（“CDR”）电路）的通道，以及标称时钟管理单元（“CMU”）电路的至少一个通道（通常包括锁相环 （“PLL”）电路等）。 为了增加可以使用信道的灵活性，标称数据处理信道被配备为交替执行CMU类型功能，并且标称CMU信道被配备为备选地执行数据处理功能。

公开(公告)号：US07855576B1

公开(公告)日：2010-12-21

申请号：US11407444

申请日：2006-04-19

申请人： Mei Luo ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Simardeep Maangat

发明人： Mei Luo ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Simardeep Maangat

IPC分类号： H03K19/0175 ,  H03K19/003

CPC分类号： H03K19/017509 ,  H04L25/0276

摘要： Methods and apparatus are provided for selectively setting a CM voltage for a transceiver, reducing the effect of current mismatch, and generating a voltage step that can be used for receiver detection. A circuit of the invention can include voltage generator circuitry operable to generate a plurality of voltage signals of substantially different voltages. The circuit can also include multiplexer circuitry with voltage inputs coupled to the voltage signals. The multiplexer circuitry can be operable to select a reference signal from among the voltage inputs. In addition, the circuit can include operational amplifier (“op-amp”) circuitry with a first input coupled to the reference signal and a second input coupled to an output signal of the op-amp circuitry.

摘要翻译： 提供了用于选择性地设置收发器的CM电压的方法和装置，减少电流失配的影响，以及产生可用于接收机检测的电压步骤。 本发明的电路可以包括可操作以产生具有实质上不同电压的多个电压信号的电压发生器电路。 电路还可以包括具有耦合到电压信号的电压输入的多路复用器电路。 多路复用器电路可以用于从电压输入中选择参考信号。 此外，电路可以包括运算放大器（“运算放大器”）电路，其中耦合到参考信号的第一输入和耦合到运放电路的输出信号的第二输入。

公开(公告)号：US07777526B2

公开(公告)日：2010-08-17

申请号：US12134777

申请日：2008-06-06

申请人： Sergey Shumarayev ,  Thungoc M. Tran ,  Wilson Wong ,  Simardeep Maangat

发明人： Sergey Shumarayev ,  Thungoc M. Tran ,  Wilson Wong ,  Simardeep Maangat

IPC分类号： H03K19/094

CPC分类号： H03K19/018514 ,  H03F3/45197 ,  H03F2203/45494 ,  H03F2203/45686

摘要： Signal offset variation caused by transistor variation/mismatch in integrated circuits may be reduced. In one embodiment, a buffer circuit has variable-valued circuit elements. Offset variation measurements are made and the variable-valued circuit elements are calibrated to reduce the measured offset variation. In another embodiment, each amplifying stage of a multi-stage buffer provides variable gain. The total DC gain of the cascade is distributed unevenly across the stages, with more DC gain being provided by amplifier stages at the beginning of the cascade than at the end. An additional pre-amplifier stage can also be provided at the beginning of the cascade.

摘要翻译： 集成电路中晶体管变化/失配引起的信号偏移变化可能会降低。 在一个实施例中，缓冲电路具有可变值电路元件。 进行偏移变化测量，并校准可变值电路元件以减少测量的偏移变化。 在另一个实施例中，多级缓冲器的每个放大级提供可变增益。 级联的总直流增益不均匀地分布在整个级中，在级联开始时比放大器级提供更多的直流增益。 在级联开始时也可以提供一个额外的前级放大器级。