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    Multi-channel communication circuitry for programmable logic device integrated circuits and the like
    5.
    发明授权
    Multi-channel communication circuitry for programmable logic device integrated circuits and the like 有权
    用于可编程逻辑器件集成电路等的多通道通信电路

    公开(公告)号：US07656187B2

    公开(公告)日：2010-02-02

    申请号：US11288810

    申请日：2005-11-28

    申请人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Tim Tri Hoang ,  Ning Xue ,  Chong Lee ,  Ramanand Venkata

    发明人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Tim Tri Hoang ,  Ning Xue ,  Chong Lee ,  Ramanand Venkata

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17736 ,  H03K19/17744

    摘要： An integrated circuit like a programmable logic device (“PLD”) includes multiple channels of data communication circuitry. Circuitry is provided for selectively sharing signals (e.g., control-type signals) among these channels in groupings of various size so that the device can better support communication protocols that require various numbers of channels (e.g., one channel operating relatively independently, four channels working together, eight channels working together, etc.). The signals shared may include a clock signal, a FIFO write enable signal, a FIFO read enable signal, or the like. The circuit arrangements are preferably modular (i.e., the same or substantially the same from one channel to the next and/or from one group of channels to the next) to facilitate such things as circuit design and verification.

    摘要翻译： 诸如可编程逻辑器件（“PLD”）的集成电路包括多个通道的数据通信电路。 提供电路用于在各种尺寸的分组中选择性地共享这些信道中的信号（例如，控制型信号），使得设备可以更好地支持需要各种信道数量的通信协议（例如，一个信道相对独立地操作，四个信道工作 一起，八个渠道在一起等）。 共享的信号可以包括时钟信号，FIFO写使能信号，FIFO读使能信号等。 电路布置优选地是模块化的（即，从一个通道到下一个通道和/或从一组通道到下一个通道相同或基本相同），以便于诸如电路设计和验证之类的事情。

    Clock circuitry for programmable logic devices
    7.
    发明授权
    Clock circuitry for programmable logic devices 有权
    可编程逻辑器件的时钟电路

    公开(公告)号：US07276936B1

    公开(公告)日：2007-10-02

    申请号：US11239702

    申请日：2005-09-29

    申请人： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev ,  In Whan Kim ,  Thungoc Tran

    发明人： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev ,  In Whan Kim ,  Thungoc Tran

    IPC分类号： H03K19/00

    CPC分类号： H03K19/1774 ,  H03K19/17744

    摘要： A programmable logic device includes high-speed serial interface (“HSSI”) circuitry that employs one or more clock signals. In addition to use of these clock signals in the HSSI circuitry, circuitry is provided for allowing at least one of these signals to be distributed throughout the PLD core circuitry, e.g., for use as an additional clock signal in the PLD core. Clock distribution is preferably done in a low-skew way.

    摘要翻译： 可编程逻辑器件包括采用一个或多个时钟信号的高速串行接口（“HSSI”）电路。 除了在HSSI电路中使用这些时钟信号之外，提供电路以允许这些信号中的至少一个分布在整个PLD核心电路中，例如用作PLD核心中的附加时钟信号。 时钟分布优选以低偏斜方式进行。

    High-speed serial data receiver architecture
    8.
    发明授权
    High-speed serial data receiver architecture 有权
    高速串行数据接收机架构

    公开(公告)号：US07702011B2

    公开(公告)日：2010-04-20

    申请号：US11361192

    申请日：2006-02-23

    申请人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Simardeep Maangat ,  Wilson Wong ,  Rakesh Patel

    发明人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Simardeep Maangat ,  Wilson Wong ,  Rakesh Patel

    IPC分类号： H03H7/30

    CPC分类号： H04L1/243 ,  H04L25/03878

    摘要： Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.

    摘要翻译： 用于包含在PLD中的串行数据信号接收器电路包括串联连接并且可单独控制的多个均衡器电路，使得它们可以统一地补偿宽范围的可能的输入信号衰减特性。 其他电路特征可以相对于均衡器电路连接以给予接收机电路其他能力。 例如，这些其他特征可以包括各种类型的环回测试电路，可控终端电阻，可控共模电压以及用于检测输入信号的可控阈值。 接收器电路的控制的各个方面可以是可编程的。

    Modular buffering circuitry for multi-channel transceiver clock and other signals
    9.
    发明授权
    Modular buffering circuitry for multi-channel transceiver clock and other signals 有权
    用于多通道收发器时钟和其他信号的模块化缓冲电路

    公开(公告)号：US07304507B1

    公开(公告)日：2007-12-04

    申请号：US11288496

    申请日：2005-11-28

    申请人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Tim Tri Hoang

    发明人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Tim Tri Hoang

    IPC分类号： H03K19/00

    CPC分类号： H03K19/17736 ,  H03K19/17744

    摘要： Circuitry for distributing signals such as reference clock signals among blocks of transceiver circuitry on an integrated circuit such as a field programmable gate array (“FPGA”) employs bidirectional buffers rather than unidirectional buffers. This allows all buffers to have the same construction regardless of physical location, which facilitates construction of the circuitry using identical or substantially identical modules. The same approach may be used for distributing other types of signals among the transceiver blocks. For example, this approach may be used for distributing calibration control signals.

    摘要翻译： 在集成电路（例如现场可编程门阵列（“FPGA”）上的收发器电路块之间分配诸如参考时钟信号的信号的电路采用双向缓冲器而不是单向缓冲器。 这允许所有缓冲器具有相同的结构，而不管物理位置如何，这有助于使用相同或基本相同的模块构建电路。 相同的方法可以用于在收发器块之间分配其他类型的信号。 例如，该方法可用于分配校准控制信号。

    Lane-to-lane skew reduction in multi-channel, high-speed, transceiver circuitry
    10.
    发明授权
    Lane-to-lane skew reduction in multi-channel, high-speed, transceiver circuitry 失效
    多通道，高速，收发器电路中的车道对车道偏斜减少

    公开(公告)号：US08649461B2

    公开(公告)日：2014-02-11

    申请号：US13299630

    申请日：2011-11-18

    申请人： Sergey Yuryevich Shumarayev

    发明人： Sergey Yuryevich Shumarayev

    IPC分类号： H04L27/00

    CPC分类号： H04L25/14

    摘要： Controllable delay circuitry is included in each channel of multi-channel, high-speed, serial transmitter and/or receiver circuitry to compensate for or to at least help compensate for possible skew (different signal propagation time) between the various channels. In systems employing CDR circuitry, the delay circuitry may be at least partly controlled by a signal derived from the CDR circuitry to make the amount of delay effected by the delay circuitry at least partly responsive to changes in data rate detected by the CDR circuitry.

    摘要翻译： 可控延迟电路包括在多通道，高速，串行发射器和/或接收器电路的每个通道中，以补偿或至少帮助补偿各个通道之间的可能的偏斜（不同的信号传播时间）。 在采用CDR电路的系统中，延迟电路可以由从CDR电路导出的信号至少部分地控制，以使由延迟电路影响的延迟量至少部分地响应由CDR电路检测到的数据速率的变化。