公开(公告)号：US09250996B2

公开(公告)日：2016-02-02

申请号：US13877650

申请日：2011-10-04

申请人： Tomoyoshi Kobori ,  Steffen Kunze ,  Emil Matus ,  Gerhard Fettweis

发明人： Tomoyoshi Kobori ,  Steffen Kunze ,  Emil Matus ,  Gerhard Fettweis

IPC分类号： G06F11/10 ,  H03M13/11 ,  H03M13/00 ,  H03M13/29 ,  H03M13/27 ,  G06F5/01

CPC分类号： G06F11/1044 ,  G06F5/015 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/114 ,  H03M13/1145 ,  H03M13/1162 ,  H03M13/1171 ,  H03M13/2775 ,  H03M13/296 ,  H03M13/2978 ,  H03M13/6508 ,  H03M13/6513 ,  H03M13/6566 ,  H03M13/6569 ,  H03M13/6577

摘要： In a multicore type error correction processing system which can simultaneously cope with a plurality of error correction methods and a plurality of code lengths, an interconnect part 11 has a barrel shifter which extends across a plurality of error correction processing parts 12a-12c. An error correction process can be selectively performed by collectively using a group of the plurality of the error correction processing parts 12a-12c or by individually using each of individual error correction processing parts 12a-12c in response to interconnection configuration information. With this structure, the plurality of the error correction processing parts 12a-12c are collectively used if computation resources are insufficient and an idling error correction processing part is assigned to another error correction process if computation resources are excessive.

摘要翻译： 在能够同时处理多个纠错方法和多个码长的多核型纠错处理系统中，互连部分11具有延伸跨越多个纠错处理部分12a-12c的桶形移位器。 可以通过集体地使用多个纠错处理部分12a-12c的组或者通过单独地使用每个单独的纠错处理部分12a-12c来响应于互连配置信息来选择性地执行纠错处理。 利用这种结构，如果计算资源不足，则多个纠错处理部分12a-12c被共同使用，并且如果计算资源过多，则将空闲纠错处理部分分配给另一纠错处理部分。

公开(公告)号：US20140040700A1

公开(公告)日：2014-02-06

申请号：US13877650

申请日：2011-10-04

申请人： Tomoyoshi Kobori ,  Steffen Kunze ,  Emil Matus ,  Gerhard Fettweis

发明人： Tomoyoshi Kobori ,  Steffen Kunze ,  Emil Matus ,  Gerhard Fettweis

IPC分类号： G06F11/10

CPC分类号： G06F11/1044 ,  G06F5/015 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/114 ,  H03M13/1145 ,  H03M13/1162 ,  H03M13/1171 ,  H03M13/2775 ,  H03M13/296 ,  H03M13/2978 ,  H03M13/6508 ,  H03M13/6513 ,  H03M13/6566 ,  H03M13/6569 ,  H03M13/6577

摘要： In a multicore type error correction processing system which can simultaneously cope with a plurality of error correction methods and a plurality of code lengths, an interconnect part 11 has a barrel shifter which extends across a plurality of error correction processing parts 12a-12c. An error correction process can be selectively performed by collectively using a group of the plurality of the error correction processing parts 12a-12c or by individually using each of individual error correction processing parts 12a-12c in response to interconnection configuration information. With this structure, the plurality of the error correction processing parts 12a-12c are collectively used if computation resources are insufficient and an idling error correction processing part is assigned to another error correction process if computation resources are excessive.

摘要翻译： 在能够同时处理多个纠错方法和多个码长的多核型纠错处理系统中，互连部分11具有延伸跨越多个纠错处理部分12a-12c的桶形移位器。 可以通过集体地使用多个纠错处理部分12a-12c的组或者通过单独地使用每个单独的纠错处理部分12a-12c来响应于互连配置信息来选择性地执行纠错处理。 利用这种结构，如果计算资源不足，则多个纠错处理部分12a-12c被共同使用，并且如果计算资源过多，则将空闲纠错处理部分分配给另一纠错处理部分。

公开(公告)号：US5978822A

公开(公告)日：1999-11-02

申请号：US581047

申请日：1995-12-29

申请人： Jumana A. Muwafi ,  Gerhard Fettweis ,  Howard W. Neff

发明人： Jumana A. Muwafi ,  Gerhard Fettweis ,  Howard W. Neff

IPC分类号： G06F5/01 ,  G06F7/76 ,  G06F7/00

CPC分类号： G06F7/762 ,  G06F5/015 ,  G06F7/768

摘要： A circuit having a single branch, which is controllable to implement either a left or right shift of bits of a data word. Preferably, the circuit is controllable to implement any selected one of the following operations: a left or right shift of bits of the word; and rotation (to the left or right) of bits of the word. In a preferred implementation, the circuit includes a set of multiplexer stages and circuitry for selectively inverting the order of the bits of the word input to, and the word output from, the set of multiplexer stages. Each of the multiplexer stages shifts the bits of the word it receives either by zero bits (in response to a first control signal), or by a positive number of bits (in response to a second control signal). By selectively controlling various subsets of the multiplexer stages, the bits of the input word can be shifted by any of a number of places (from zero to N, where N is some positive number). In another aspect, the invention is a circuit for rotating bits of an input word (by two or more bits to the left or right) during a single cycle, by duplicating the input word to form an extended word, shifting bits of the extended word, and selecting a subset of the shifted bits of the extended word. Other aspects of the invention are methods performed by, and a digital signal processor including, either embodiment of the inventive circuit.

摘要翻译： 具有单个分支的电路，其可控制以实现数据字的位的左移或右移。 优选地，电路是可控制的，以实现以下操作中的任何选择的一个：字的位的左移或右移; 以及字的位的旋转（向左或向右）。 在优选的实施方案中，电路包括一组多路复用器级和电路，用于选择性地反转字输入的位的顺序和多路复用器级的集合输出的字。 多路复用器级中的每一个通过零位（响应于第一控制信号）或通过正数位（响应于第二控制信号）来移位其接收的字的位。 通过选择性地控制多路复用器级的各个子集，可以通过多个位置（从零到N，其中N是一些正数）中的任意一个来移位输入字的位。 另一方面，本发明是一种电路，用于在单个周期期间通过复制输入字以形成扩展字来转换输入字的位（向左或向右两位或更多位），从而使扩展字的位移位 ，并且选择扩展字的移位位的子集。 本发明的其他方面是由本发明的电路的任一实施例执行的方法和数字信号处理器。

公开(公告)号：US20130064163A1

公开(公告)日：2013-03-14

申请号：US13606283

申请日：2012-09-07

申请人： Gerhard Fettweis ,  Walter Nitzold ,  Stefan Krone ,  Trevor Gill

发明人： Gerhard Fettweis ,  Walter Nitzold ,  Stefan Krone ,  Trevor Gill

IPC分类号： H04W4/06

CPC分类号： H04L1/1854 ,  H04L1/1861 ,  H04L1/188 ,  H04L2001/0093

摘要： A radio communication system comprises an access station that is adapted and configured to transmit a rateless encoded multicast message to a plurality of radio terminals. Each of the radio terminals transmits a reply message to the access station upon successful reception of the multicast message, wherein the transmit resources are selected from a predefined set of agreed transmit resources, where the selection is influenced by certain characteristics of the reception of the multicast message.

摘要翻译： 无线电通信系统包括接入站，其适于并配置为向多个无线电终端发送无编码编码的多播消息。 每个无线电终端在成功接收到多播消息后，向接入站发送回复消息，其中从预定义的一组约定的发送资源中选择发送资源，其中选择受到组播的接收的某些特性的影响 信息。

公开(公告)号：US20100296556A1

公开(公告)日：2010-11-25

申请号：US12808171

申请日：2008-12-12

申请人： Wolfgang Rave ,  Andre Fonseca Dos Santos ,  Gerhard Fettweis

发明人： Wolfgang Rave ,  Andre Fonseca Dos Santos ,  Gerhard Fettweis

IPC分类号： H04L27/01 ,  H04B1/38

CPC分类号： H04L25/03171 ,  H04L25/0212 ,  H04L25/0238

摘要： A method and a corresponding system for estimating and refining channel tap values for use in an equalizer on the receiver side, wherein the method is based on exploiting statistics of logic strings that multilevel codes impose on a transmitted signal.

摘要翻译： 一种用于估计和提炼在接收机侧的均衡器中使用的信道抽头值的方法和相应的系统，其中该方法基于利用多级代码对发射信号施加的逻辑串的统计。

公开(公告)号：US08774161B2

公开(公告)日：2014-07-08

申请号：US13175781

申请日：2011-07-01

申请人： Gerhard Fettweis ,  Peter Rost ,  Walter Nitzold

发明人： Gerhard Fettweis ,  Peter Rost ,  Walter Nitzold

IPC分类号： H04B7/212

CPC分类号： H04W72/048 ,  H04W16/14 ,  H04W28/26

摘要： A communication method for a mobile communication system is described. Available radio resources, i.e. an available frequency band, are divided into a plurality of comparatively small radio resource units. The mobile communication system uses a first communication protocol for communicating with mobile stations compatible with the mobile communication system. For communicating with an autonomous terminal at least one radio resource unit is allocated, in which a second communication protocol incompatible with the first communication protocol is used for communicating with the terminal.

摘要翻译： 对移动通信系统的通信方法进行说明。 可用的无线电资源，即可用的频带，被分成多个较小的无线电资源单元。 移动通信系统使用第一通信协议来与移动通信系统兼容的移动站进行通信。 为了与自主终端通信，分配至少一个无线电资源单元，其中与第一通信协议不兼容的第二通信协议用于与终端进行通信。

公开(公告)号：US20120002644A1

公开(公告)日：2012-01-05

申请号：US13175781

申请日：2011-07-01

申请人： Gerhard Fettweis ,  Peter Rost ,  Walter Nitzold

发明人： Gerhard Fettweis ,  Peter Rost ,  Walter Nitzold

IPC分类号： H04W72/04

CPC分类号： H04W72/048 ,  H04W16/14 ,  H04W28/26

摘要： A communication method for a mobile communication system is described. Available radio resources, i.e. an available frequency band, are divided into a plurality of comparatively small radio resource units. The mobile communication system uses a first communication protocol for communicating with mobile stations compatible with the mobile communication system. For communicating with an autonomous terminal at least one radio resource unit is allocated, in which a second communication protocol incompatible with the first communication protocol is used for communicating with the terminal.

摘要翻译： 对移动通信系统的通信方法进行说明。 可用的无线电资源，即可用的频带，被分成多个较小的无线电资源单元。 移动通信系统使用第一通信协议来与移动通信系统兼容的移动站进行通信。 为了与自主终端通信，分配至少一个无线电资源单元，其中与第一通信协议不兼容的第二通信协议用于与终端进行通信。

公开(公告)号：US07069418B2

公开(公告)日：2006-06-27

申请号：US10075916

申请日：2002-02-14

申请人： Matthias Weiss ,  Gerhard Fettweis

发明人： Matthias Weiss ,  Gerhard Fettweis

IPC分类号： G06F9/44

CPC分类号： G06F9/3814 ,  E04G21/0436 ,  E04G21/0463 ,  G06F9/3017 ,  G06F9/3802 ,  G06F9/3853

摘要： The invention relates to a method and an arrangement for instruction word generation in the controlling of functional units in a processor, the instruction words comprising a plurality of instruction word parts. In this case, in a program sequence, under the control of a program word, an instruction word is taken from a row—determined by a reading row number—of an instruction word memory that can be written to row by row, the said instruction word is altered by means of substitution of an instruction word part by the information part of the respective program word and is written back to a row of the instruction word memory, the said row being determined by a writing row number. Afterwards, an instruction word—which is generated in this way and is to be executed in accordance with the program—for controlling the functional units is output to the processor.According to the invention, a reduction in the processing width and an increase in the operating speed is achieved by the writing and reading row numbers being generated by corresponding registers and/or the largest possible number of instruction words that are to be executed being successively compiled in the instruction word memory and processed, so that they are combined in blocks. This makes it possible to reduce the processing width during the program word processing in the part which carries control information.

摘要翻译： 本发明涉及一种在处理器中对功能单元的控制中的指令字生成的方法和装置，所述指令字包括多个指令字部分。 在这种情况下，在程序序列中，在程序字的控制下，从可以被逐行写入的指令字存储器的读取行数确定的行中取出指令字，所述指令 通过由相应程序字的信息部分替换指令字部分来改变字，并将其写回指令字存储器的一行，所述行由写入行号确定。 之后，向处理器输出以这种方式生成并根据用于控制功能单元的程序执行的指令字。 根据本发明，通过由对应的寄存器生成的写入和读取行号和/或要被执行的最大可能数量的指令字被连续编译来实现处理宽度的减小和操作速度的增加 在指令字存储器中进行处理，使它们以块为单位组合。 这使得可以在携带控制信息的部分中减少程序文字处理期间的处理宽度。

公开(公告)号：US5710914A

公开(公告)日：1998-01-20

申请号：US581320

申请日：1995-12-29

申请人： Ingrid Verbauwhede ,  Gerhard Fettweis

发明人： Ingrid Verbauwhede ,  Gerhard Fettweis

IPC分类号： G06F9/315 ,  G06F9/38 ,  G06F9/34 ,  G06F9/42

CPC分类号： G06F9/3885 ,  G06F9/30032 ,  G06F9/3824 ,  G06F9/3867

摘要： A digital signal processing system and method for executing instructions with decode, read, execute, and write pipeline cycles. In the decode cycle, control signals are generated which determine addresses which in turn determine memory locations from which data are to be read and to which processed data are to be written. The system includes a program control unit for processing a sequence of instructions and controlling system operation, a memory, a data processing unit, and a dedicated bus for writing processed data from the data processing unit to the memory. By using a dedicated write bus, the system avoids bus contention in a five stage pipeline operation involving fetch, decode, read, execute, and write operations. A post shift unit connected along the write bus shifts data values that have been output from the data processing unit before they are written to the memory. The system also executes instructions in a pipelined manner, in which addresses for reads from a memory are asserted on an address bus in one pipeline cycle and addresses for writes to the memory are asserted on the address bus in a different pipeline cycle.

摘要翻译： 一种用于执行具有解码，读取，执行和写入流水线循环的指令的数字信号处理系统和方法。 在解码周期中，产生控制信号，这些控制信号确定地址，这些地址又决定要从哪个数据被读取的存储器位置以及哪个被处理的数据被写入。 该系统包括用于处理指令序列和控制系统操作的程序控制单元，存储器，数据处理单元以及用于将处理后的数据从数据处理单元写入存储器的专用总线。 通过使用专用写总线，系统避免了涉及获取，解码，读取，执行和写入操作的五级流水线操作中的总线争用。 沿着写总线连接的移位单元在数据处理单元被写入存储器之前移位已经输出的数据值。 系统还以流水线方式执行指令，其中在一个流水线周期中在地址总线上断言来自存储器的读取地址，并且在不同流水线周期的地址总线上断言用于写入存储器的地址。

公开(公告)号：US5452466A

公开(公告)日：1995-09-19

申请号：US60228

申请日：1993-05-11

申请人： Gerhard Fettweis

发明人： Gerhard Fettweis

IPC分类号： G06F7/76 ,  G06F17/14 ,  G06T9/00

CPC分类号： G06F7/762 ,  G06F17/147 ,  G06T9/007

摘要： A method and apparatus for implementing a discrete cosine transform (DCT) or an inverse DCT (IDCT) with a single hardware unit which applies only positive valued multiplicative coefficients and can be switched to either perform a DCT or an IDCT. The invention processes parallel input digital data signals to produce parallel output digital data signals which represent a discrete transform (either a DCT or an IDCT) of the input data. One aspect of the invention is a method and apparatus for performing discrete transforms using a multiplier which implements MSB-first, bit-serial, carry-save, multiplication of an input word by a positive fixed coefficient. In one class of embodiments, the serially received digits of the input word can take on positive values only. In other embodiments, the serially received digits of the input word can take on positive or negative values. Performance of MSB-first carry-save multiplication allows the design of extremely efficient transforming hardware having low processing delay and high precision, and supporting medium to low speed transform rates. Another aspect of the invention is a method and apparatus for performing discrete transforms using a butterfly addition/subtraction circuit which receives two serial signals and generates both the sum and difference of such signals. In one class of embodiments, the inventive butterfly addition/subtraction circuit implements MSB-first, bit-serial addition and subtraction. In other embodiments, the inventive butterfly addition/subtraction circuit implements LSB-first, bit-serial addition and subtraction.

摘要翻译： 用于仅使用正值乘法系数的单个硬件单元来实现离散余弦变换（DCT）或逆DCT（IDCT）的方法和装置，并且可以切换到执行DCT或IDCT。 本发明处理并行输入数字数据信号以产生表示输入数据的离散变换（DCT或IDCT）的并行输出数字数据信号。 本发明的一个方面是一种使用乘法器执行离散变换的方法和装置，该乘法器以一个正的固定系数实现了输入字的MSB优先，位串行，进位 - 保存，乘法运算。 在一类实施例中，输入字的串行接收数字只能取正值。 在其他实施例中，输入字的串行接收数字可以取正或负值。 MSB优先进行保存乘法的性能允许设计具有低处理延迟和高精度的极其有效的转换硬件，并支持中低速变换速率。 本发明的另一方面是一种使用接收两个串行信号并产生这些信号的和和差分的蝶形加/减电路来执行离散变换的方法和装置。 在一类实施例中，本发明的蝶形加法/减法电路实现MSB优先，比特串行加法和减法。 在其他实施例中，本发明的蝶形加/减电路实现了LSB优先，位串行加法和减法。