Abstract:
A structure of a semiconductor device facilitating electrostatic discharge protection at least includes a source terminal, a drain terminal, and a gate terminal, wherein a portion of the source terminal and a portion of the drain terminal are overlapped above the gate terminal to increase the coupling capacitance so that the electrostatic discharge protection device can be turned on quickly. Accordingly the response of the electrostatic discharge protection device to an electrostatic discharge can be effectively promoted.
Abstract:
A low-temperature polysilicon thin film transistor having a buried LDD structure is provided. Two heavily doped regions are formed in a semiconductor layer and distributed just below a surface of the semiconductor layer. Two LDD regions are both sandwiched between the two heavily doped regions in a direction substantially parallel to the surface of semiconductor layer, and separated from the surface of the semiconductor layer by a portion of the semiconductor layer. The process for producing such a thin film transistor is also provided. A first, a second and a third doping materials are injected into a semiconductor layer in different directions to form heavily doped regions and LDD regions.
Abstract:
A thin film transistor having a single LDD structure with a halo structure is provided. The single LDD structure is disposed between source/drain structures, and having a first side adjacent to a first one of the source/drain structures and a second side spaced from a second one of the source/drain structures by essentially a semiconductor material. The halo structure is adjacent to the LDD structure partially or largely covering the LDD structure.
Abstract:
A liquid crystal display (LCD) interface that includes a plurality of first transmission lines including N sets of transmission lines, each set of the first transmission lines being associated with a pixel formed in the LCD device, and a plurality of second transmission lines, each being coupled to one the plurality of first transmission lines, the plurality of second transmission lines including a plurality of sets, alternating in odd-numbered and even-numbered sets, each set of the second transmission lines corresponding to the plurality of first transmission lines, and each set including a plurality of subsets, each being associated with a pixel formed in the LCD device, wherein an M-th subset of each of the odd-numbered sets of the second transmission lines is coupled to an M-th set of the first transmission lines, and an M-th subset of each of the even-numbered sets of the second transmission lines is coupled to an (NnullMnull1)-th set of the first transmission lines, M being an integral between 1 and N.
Abstract:
A structure of a thin film transistor (TFT) planar display panel is disclosed. The structure includes a light-transmissible substrate, a buffer layer formed on the light-transmissible substrate, a top-gate TFT structure formed on the buffer layer and including a channel region, and a light-shielding structure formed between a back light source and the top-gate TFT structure, and substantially aligned with the channel region for protecting the channel region from illumination of the back light source. The process for manufacturing a TFT planar display panel is also disclosed.
Abstract:
An ESD protection circuit for low temperature poly-silicon thin film transistor panel and a display panel using the same. The feature of the ESD protection circuit comprises an ESD detection circuit disposed between a first power line and a second power line, for outputting an enable signal when an ESD event occurs in the first power line; and a discharge device having a control terminal coupled to the output of the ESD detection circuit, for providing a discharge path between the first and second power lines when the control terminal receives the enable signal.
Abstract:
A low-temperature polysilicon thin film transistor having a buried LDD structure is provided. Two heavily doped regions are formed in a semiconductor layer and distributed just below a surface of the semiconductor layer. Two LDD regions are both sandwiched between the two heavily doped regions in a direction substantially parallel to the surface of semiconductor layer, and separated from the surface of the semiconductor layer by a portion of the semiconductor layer. The process for producing such a thin film transistor is also provided. A first, a second and a third doping materials are injected into a semiconductor layer in different directions to form heavily doped regions and LDD regions.
Abstract:
A pixel testing method is provided. The pixel testing method is adapted to measure device parameters within each pixel of a display. Before plating a lighting device into each pixel, a capacitor is formed such that one end of the capacitor is connected to an open-circuit terminal of an electronic device while the other end of the capacitor is connected to an added common line (or the original scan line or data line of the display). The parameters of the electronic device connected to the lighting device are tested through a charging/discharging of the capacitor so that all the devices within a pixel can be tested before forming organic functional layer in every pixel.
Abstract:
In a process for forming a thin film transistor, a gate insulator layer is formed on a semiconductor layer. A gate structure is formed on the gate insulator layer, and source/drain structures are formed in the semiconductor layer. The source/drain structures are spaced from each other by a channel region. A first kind of doping material is injected into a first end portion of the channel region in a first direction of a first angle from a surface of the semiconductor layer to form a first LDD structure, and a second kind of doping material is injected into the first end portion of the channel region in a second direction of a second angle from the surface of the semiconductor layer to form a first halo structure in contact with the first LDD structure.
Abstract:
A thin film transistor having a single LDD structure is provided. The single LDD structure is disposed between source/drain structures, and having a first side adjacent to a first one of the source/drain structures and a second side spaced from a second one of the source/drain structures by essentially a semiconductor material. Another thin film transistor having a first kind of LDD and a second kind of LDD structure is also provided. The second kind of LDD structure is adjacent to the first kind of LDD structure. The process for manufacturing such thin film transistor is also disclosed.