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42 条记录 (耗时 0.026 秒)

    Customized personal terminal device
    2.
    发明授权
    Customized personal terminal device 失效
    定制个人终端设备

    公开(公告)号：US5163111A

    公开(公告)日：1992-11-10

    申请号：US567010

    申请日：1990-08-14

    申请人： Toru Baji ,  Kouki Noguchi ,  Tetsuya Nakagawa ,  Motonobu Tonomura ,  Hajime Akimoto ,  Toshiaki Masuhara

    发明人： Toru Baji ,  Kouki Noguchi ,  Tetsuya Nakagawa ,  Motonobu Tonomura ,  Hajime Akimoto ,  Toshiaki Masuhara

    IPC分类号： G06F15/18 ,  G06F3/00 ,  G06F3/16 ,  G06F15/00 ,  G06F15/02 ,  G06K9/52 ,  G06N3/00 ,  G06N99/00 ,  G07C9/00 ,  G10L15/06 ,  G10L15/16

    CPC分类号： G10L15/16 ,  G06F3/16 ,  G06K9/522 ,  G07C9/00071 ,  G06K2209/01

    摘要： There is provided a customized personal terminal device capable of operating in response to input data peculiar to the operator, comprising a speech recognition unit for recognizing inputted speech, an image recognition unit for recognizing inputted image, and an instruction recognition unit for recognizing an inputted instruction. Neural networks are provided in at least two of the speech, image and instruction recognition units, a bus operatively connected to the respective recognition units, a processor operatively connected to the bus to perform processing upon the speech, and image and instruction recognized by the recognition units. Also, memory is operatively connected to the bus, and a control unit exercises control over information exchange between respective recognition units and the memory under the control of the processor.

    摘要翻译： 提供了能够响应于操作者特有的输入数据而操作的定制个人终端装置，包括用于识别输入的语音的语音识别单元，用于识别输入的图像的图像识别单元，以及用于识别输入的指令的指令识别单元 。 神经网络提供在语音，图像和指令识别单元中的至少两个中，可操作地连接到各个识别单元的总线，可操作地连接到总线以对语音执行处理的处理器，以及通过识别识别的图像和指令 单位。 此外，存储器可操作地连接到总线，并且控制单元在处理器的控制下对各个识别单元和存储器之间的信息交换进行控制。

    Semiconductor memory with divided bit load and data bus lines
    3.
    发明授权
    Semiconductor memory with divided bit load and data bus lines 失效

    公开(公告)号：US4935901A

    公开(公告)日：1990-06-19

    申请号：US158259

    申请日：1988-02-19

    申请人： Toshio Sasaki ,  Osamu Minato ,  Shigeru Honjiyo ,  Koichiro Ishibashi ,  Toshiaki Masuhara

    发明人： Toshio Sasaki ,  Osamu Minato ,  Shigeru Honjiyo ,  Koichiro Ishibashi ,  Toshiaki Masuhara

    IPC分类号： G11C11/419

    CPC分类号： G11C11/419

    摘要： A static RAM memory is divided into a plurality of mats (12). Word lines (16) in each pair of mats are accessed by an x-decoder (14). Columns or bit lines are accessed by a y-decoder (20) which selectively connect pairs of bit lines (22) to common data bus segments (24). Transistors (60, 62) connect selected bit lines with a load during a write cycle to stabilize those bit lines and memory cells into which data is written. The x-decoders are connected with near word lines (16a) for addressing a near half of each mat and are operatively connected with remote word lines (16b) for addressing word lines in a remote half of each mat. In this manner, each mat is divided into two effective mats. The bit lines of all the effective mats within an actual mat are connected with the same output data bus segment. A pair of sensing amplifiers (32) is provided for each bit of memory which is accessed concurrently, e.g. eight bits, such that the high and low output of each flip-flop memory cell (18) are both amplified. A pair of driving amplifiers (34) further amplify each high and low output before applying them to an output data bus (38).

    Electron device
    7.
    发明授权
    Electron device 失效
    电子器件

    公开(公告)号：US4089022A

    公开(公告)日：1978-05-09

    申请号：US744864

    申请日：1976-11-24

    申请人： Shojiro Asai ,  Toshiaki Masuhara ,  Kenji Kaneko

    发明人： Shojiro Asai ,  Toshiaki Masuhara ,  Kenji Kaneko

    IPC分类号： H01L21/822 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/06 ,  H01L27/082 ,  H01L27/088 ,  H01L29/73 ,  H01L29/78 ,  H03K19/082

    CPC分类号： H01L27/088 ,  H01L27/082 ,  H01L29/7304

    摘要： An electron device comprising (i) a semiconductor element which includes a semiconductor region A of a first conductivity type, a semiconductor region B of a second conductivity type adjoining the region A, and a semiconductor region C of the second conductivity type adjoining the region A and isolated from the region B by the region A, and in which on a surface extending from the region B via the region A to the region C, a gate electrode is provided through an insulating film, (ii) means for holding a potential of the gate electrode so that a potential of minority carriers in a surface portion of the region A underneath the gate electrode may become lower than a potential in an inner portion of the region A, (iii) means for applying a forward bias voltage between the region A and the region B, and (iv) means for applying to the region C a potential by which a potential for the minority carriers becomes lower in the region C than in the region B. The electron device is capable of such operations as amplification, oscillation and memory under an extraordinarily low supply voltage, and is extraordinarily low in the power consumption.

    摘要翻译： 一种电子器件，包括（i）半导体元件，其包括第一导电类型的半导体区域A，与区域A相邻的第二导电类型的半导体区域B和与区域A相邻的第二导电类型的半导体区域C 并且通过区域A从区域B隔离，并且其中在从区域B经由区域A延伸到区域C的表面上，通过绝缘膜提供栅电极，（ii）保持电位的装置 使得栅极电极下面的区域A的表面部分中的少数载流子的电位可能变得低于区域A的内部部分中的电位，（iii）在区域A之间施加正向偏置电压的装置 A和区域B，以及（iv）用于向区域C施加在区域C中少于少数载流子的电位低于区域B的电位的装置。电子装置能够 作为在非常低的电源电压下的放大，振荡和存储的操作，并且功耗非常低。

    Semiconductor device and a method for fabricating the same
    8.
    发明授权
    Semiconductor device and a method for fabricating the same 失效
    半导体装置及其制造方法

    公开(公告)号：US4021835A

    公开(公告)日：1977-05-03

    申请号：US544265

    申请日：1975-01-27

    申请人： Jun Etoh ,  Toshiaki Masuhara

    发明人： Jun Etoh ,  Toshiaki Masuhara

    IPC分类号： H01L21/265 ,  H01L29/78

    CPC分类号： H01L29/7838 ,  H01L21/2652 ,  H01L29/78

    摘要： A MOS-FET (Metal-Oxide-Semiconductor Field Effect Transistor) comprises a semiconductor body, source and drain regions disposed in the body at portions separated from each other, a second semiconductor region having a higher impurity concentration than that of the body, formed by ion implantation in the body between the source and drain regions, a first semiconductor region having a lower impurity concentration than that of the second semiconductor region but a higher impurity concentration than that of the body, and having an opposite conductivity type to that of the second semiconductor region, formed by ion implantation, so that the second semiconductor region is very thin, and which has a very small amount of a minute current, that is a tailing current.

    摘要翻译： MOS-FET（金属氧化物半导体场效应晶体管）包括半导体本体，源极和漏极区域，其设置在彼此分离的部分的主体中，形成具有比主体杂质浓度更高的第二半导体区域 通过在源极和漏极区域之间的体内离子注入，具有比第二半导体区域低的杂质浓度的杂质浓度较低的杂质浓度比第二半导体区域低的杂质浓度的第一半导体区域，并且具有与 第二半导体区域，通过离子注入形成，使得第二半导体区域非常薄，并且具有非常少量的微小电流，即尾部电流。

    Semiconductor device
    10.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US4864382A

    公开(公告)日：1989-09-05

    申请号：US148052

    申请日：1988-01-25

    申请人： Masaaki Aoki ,  Kazuo Yano ,  Toshiaki Masuhara

    发明人： Masaaki Aoki ,  Kazuo Yano ,  Toshiaki Masuhara

    IPC分类号： H01L27/108 ,  H01L29/10 ,  H01L29/167 ,  H01L29/66

    CPC分类号： H01L29/66992 ,  H01L27/10805 ,  H01L29/1083 ,  H01L29/167 ,  Y10S257/919

    摘要： A MOS memory is formed in a semiconductor bulk, whereas a barrier semiconductor layer is disposed at the boundary between a MOS memory portion and the semiconductor bulk in order to reduce the effect of undesirable carriers excited by .alpha.-particles. The barrier semiconductor layer is designed to permit operation of the memory at low temperature while reducing the incidence of soft errors due to .alpha.-particles.

    摘要翻译： 在半导体本体中形成MOS存储器，而在MOS存储器部分和半导体体之间的边界处设置阻挡半导体层，以便降低由α-粒子激发的不希望的载流子的影响。 阻挡半导体层被设计为允许在低温下操作存储器，同时减少由于α-粒子引起的软错误的发生。