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1.发明授权Method of manufacturing semiconductor integrated circuit devices having a memory device with a reduced bit line stray capacity and such semiconductor integrated circuit devices 失效具有具有降低的位线杂散容量的存储器件的半导体集成电路器件的制造方法以及这种半导体集成电路器件公开(公告)号：US06969649B2
公开(公告)日：2005-11-29
申请号：US10810884
申请日：2004-03-29
申请人： Toshihiro Sekiguchi , Yoshitaka Tadaki , Keizo Kawakita , Hideo Aoki , Toshikazu Kumai , Kazuhiko Saito , Michio Nishimura , Michio Tanaka , Katsuo Yuhara , Shinya Nishio , Toshiyuki Kaeriyama , Songsu Cho
发明人： Toshihiro Sekiguchi , Yoshitaka Tadaki , Keizo Kawakita , Hideo Aoki , Toshikazu Kumai , Kazuhiko Saito , Michio Nishimura , Michio Tanaka , Katsuo Yuhara , Shinya Nishio , Toshiyuki Kaeriyama , Songsu Cho
IPC分类号： H01L21/8242 , H01L21/60 , H01L27/108
CPC分类号： H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.
摘要翻译： 在一个实施例中，DRAM具有其上表面和侧表面被第一绝缘膜覆盖的多个字线，多个位线设置成与字线绝缘并横向于字线并被覆盖 具有第二绝缘膜和多个存储单元，每个存储单元设置在一个字线和一个位线之间的交点处，并且包括电容器和存储单元选择晶体管，其中用于在半导体区域和电容器之间以及半导体之间连接的接触孔 区域和位线形成为自对准，并且第二绝缘膜由电容率小于第一绝缘膜的介电常数的材料制成。
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2.发明授权Method of manufacturing semiconductor integrated circuit devices having a memory device with a reduced bit line stray capacity and such semiconductor integrated circuit devices 有权具有具有降低的位线杂散容量的存储器件的半导体集成电路器件的制造方法以及这种半导体集成电路器件公开(公告)号：US06753219B2
公开(公告)日：2004-06-22
申请号：US10226290
申请日：2002-08-23
申请人： Toshihiro Sekiguchi , Yoshitaka Tadaki , Keizo Kawakita , Hideo Aoki , Toshikazu Kumai , Kazuhiko Saito , Michio Nishimura , Michio Tanaka , Katsuo Yuhara , Shinya Nishio , Toshiyuki Kaeriyama , Songsu Cho
发明人： Toshihiro Sekiguchi , Yoshitaka Tadaki , Keizo Kawakita , Hideo Aoki , Toshikazu Kumai , Kazuhiko Saito , Michio Nishimura , Michio Tanaka , Katsuo Yuhara , Shinya Nishio , Toshiyuki Kaeriyama , Songsu Cho
IPC分类号： H01L218242
CPC分类号： H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.
摘要翻译： 在一个实施例中，DRAM具有其上表面和侧表面被第一绝缘膜覆盖的多个字线，多个位线设置成与字线绝缘并横向于字线并被覆盖 具有第二绝缘膜和多个存储单元，每个存储单元设置在一个字线和一个位线之间的交点处，并且包括电容器和存储单元选择晶体管，其中用于在半导体区域和电容器之间以及半导体之间连接的接触孔 区域和位线形成为自对准，并且第二绝缘膜由电容率小于第一绝缘膜的介电常数的材料制成。
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3.发明授权Method of manufacturing semiconductor integrated circuit devices using phase shifting mask 失效使用相移掩模制造半导体集成电路器件的方法
公开(公告)号：US5937290A
公开(公告)日：1999-08-10
申请号：US862992
申请日：1997-05-27
申请人： Toshihiro Sekiguchi , Yoshitaka Tadaki , Keizo Kawakita , Katsuo Yuhara , Kazuhiko Saito , Shinya Nishio , Michio Tanaka , Michio Nishimura , Toshiyuki Kaeriyama , Songsu Cho
发明人： Toshihiro Sekiguchi , Yoshitaka Tadaki , Keizo Kawakita , Katsuo Yuhara , Kazuhiko Saito , Shinya Nishio , Michio Tanaka , Michio Nishimura , Toshiyuki Kaeriyama , Songsu Cho
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , Y10S438/942
摘要： In an embodiment of a method of manufacturing semiconductor integrated circuit devices according to the present invention, word lines are provided in a straight form, which serve as gate electrodes of two selecting MOSFETs formed symmetrical about a center portion of an active region surrounded by a LOCOS oxide film on a semiconductor substrate, and bit lines have straight segments and protruding segments. Each protruding segment is formed to protrude from the bit line and is connected through a first contact hole to a first semiconductor region formed at the center portion of the active region. The straight line segments and the protruding segments are formed separately by two separate exposure steps.
摘要翻译： 在根据本发明的制造半导体集成电路器件的方法的实施例中，字线被提供成直线形式，其用作两个选择MOSFET的栅电极，所述选择MOSFET形成为由LOCOS包围的有源区域的中心部分对称地形成 半导体衬底上的氧化膜，位线具有直段和突出段。 每个突出部分形成为从位线突出，并且通过第一接触孔连接到形成在有源区域的中心部分处的第一半导体区域。 直线段和突出段通过两个单独的曝光步骤分别形成。
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公开(公告)号：USD427110S
公开(公告)日：2000-06-27
申请号：US110206
申请日：1999-09-02
申请人： Kazuhiko Saito , Kazuhiko Yokoyaya
设计人： Kazuhiko Saito , Kazuhiko Yokoyaya
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公开(公告)号：USD298744S
公开(公告)日：1988-11-29
申请号：US895058
申请日：1986-08-11
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公开(公告)号：USD295395S
公开(公告)日：1988-04-26
申请号：US712058
申请日：1985-03-15
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公开(公告)号：US09125265B2
公开(公告)日：2015-09-01
申请号：US13569945
申请日：2012-08-08
申请人： Hiroyuki Kojima , Noriaki Okada , Kazuhiko Saito , Shuhei Kawai , Feng Xu
发明人： Hiroyuki Kojima , Noriaki Okada , Kazuhiko Saito , Shuhei Kawai , Feng Xu
CPC分类号： H05B33/0818 , H05B33/0851
摘要： In a control circuit for a light-emitting device, a reference voltage generation circuit detects a full-wave rectified voltage and generates a first voltage as well as generating a second voltage by converting the rectified voltage into a DC voltage. A voltage corresponding to a difference between the first voltage and the second voltage or a voltage corresponding to a ratio of the first voltage to the second voltage is generated as a reference voltage by a subtraction circuit or by a division circuit, respectively. As a result, a change in amplitude of the reference voltage can be suppressed when amplitude of the rectified voltage is varied due to a variation in an AC input voltage supplied from an AC power supply.
摘要翻译： 在发光装置的控制电路中，参考电压产生电路检测全波整流电压，并通过将整流电压转换成直流电压来产生第一电压以及产生第二电压。 相应于第一电压和第二电压之间的差的电压或对应于第一电压与第二电压的比率的电压分别由减法电路或分频电路产生作为参考电压。 结果，由于由交流电源供给的交流输入电压的变化，整流电压的振幅变化，可以抑制基准电压的振幅的变化。
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公开(公告)号：US06713979B2
公开(公告)日：2004-03-30
申请号：US10201972
申请日：2002-07-25
申请人： Hayato Naito , Noriaki Okada , Kazuhiko Saito
发明人： Hayato Naito , Noriaki Okada , Kazuhiko Saito
IPC分类号： H02P314
摘要： In the invention, pairs of output transistors are provided. An actuator having an inductance is connected to nodes formed between the pairs of output transistors. A drive circuit for the actuator is arranged such that the actuator is driven by causing a drive current to flow into the inductance. The drive circuit has an overvoltage detection circuit for detecting whether or not a voltage appearing at the nodes of the output transistor pairs exceeds a supply voltage by a first predetermined level and whether or not the voltage becomes lower than a ground level by a second predetermined level. Output transistors connected to the nodes are activated by an output from the overvoltage detection circuit.
摘要翻译： 在本发明中，提供了输出晶体管对。 具有电感的致动器连接到形成在输出晶体管对之间的节点。 用于致动器的驱动电路被布置成使得致动器通过使驱动电流流入电感而被驱动。 驱动电路具有过电压检测电路，用于检测出现在输出晶体管对的节点处的电压是否超过第一预定电平的电源电压以及电压是否低于接地电平第二预定电平 。 连接到节点的输出晶体管由过电压检测电路的输出激活。
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9.发明授权Symmetric/asymmetric shared processing operation in a tightly coupled multiprocessor 失效紧密耦合的多处理器中的对称/非对称共享处理操作
公开(公告)号：US5649184A
公开(公告)日：1997-07-15
申请号：US495982
申请日：1990-03-20
申请人： Katsumi Hayashi , Masaaki Mitani , Yutaka Sekine , Tomohiro Hayashi , Kazuhiko Saito , Yoshinori Shimogai
发明人： Katsumi Hayashi , Masaaki Mitani , Yutaka Sekine , Tomohiro Hayashi , Kazuhiko Saito , Yoshinori Shimogai
CPC分类号： G06F9/524 , Y10S707/922 , Y10S707/99938
摘要： In a data base processing system using a multiprocessor system, the data base processing system includes: a storage unit provided in the shared memory for storing data base management information representing either an object of a shared processing operation or an object of a local processing operation for every resource; an access management unit provided in each of the processor modules for performing an access control for an access request to the data base under either the shared processing operation or the local processing operation in accordance with the data base management information, the shared processing operation being symmetrically performed, and the local processing operation being asymmetrically performed in each processor module; and a control unit provided in the processor module for controlling the shared/local conversion in such a way that: an access state of the resource is managed for every resource; when a frequency of the access is unevenly distributed to a particular processor module, the resource of that processor module is determined as the object of the local processing operation at that particular processor module; and when the frequency of the access is not unevenly distributed to a particular processor module, the resource of a particular processor module is determined as the object of the shared processing operation. The data base processing system further includes a deadlock detection system.
摘要翻译： 在使用多处理器系统的数据库处理系统中，数据库处理系统包括：存储单元，设置在共享存储器中，用于存储表示共享处理操作的对象或本地处理操作的对象的数据库管理信息， 每个资源; 在每个处理器模块中设置的访问管理单元，用于根据数据库管理信息在共享处理操作或本地处理操作下执行对数据库的访问请求的访问控制，共享处理操作对称地 并且在每个处理器模块中不对称地执行本地处理操作; 以及控制单元，设置在所述处理器模块中，用于以如下方式控制所述共享/本地转换：对每个资源管理所述资源的访问状态; 当访问频率不均匀地分配给特定处理器模块时，该处理器模块的资源被确定为该特定处理器模块处的本地处理操作的对象; 并且当访问的频率不是不均匀地分配给特定处理器模块时，特定处理器模块的资源被确定为共享处理操作的对象。 数据库处理系统还包括死锁检测系统。
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10.发明授权Magnetic disk apparatus and method with actuator control using servo sector information read out at particular timings 失效磁盘装置和方法，其具有使用伺服扇区信息的致动器控制，在特定定时读出
公开(公告)号：US5473482A
公开(公告)日：1995-12-05
申请号：US136231
申请日：1993-10-15
申请人： Kazuhiko Saito , Toshiyuki Okawa
发明人： Kazuhiko Saito , Toshiyuki Okawa
CPC分类号： G11B5/596
摘要： A magnetic disc apparatus controls the output timing of control current data by use of a servo estimation type observer. Servo information is read from a servo sector of a magnetic disc, decoded, and used to calculate control current data. Before the servo information of the following servo sector is fully decoded, the calculated control current data from the previously read servo sector is output, converted to a current, and sent to the actuator of a magnetic head.
摘要翻译： 磁盘装置通过使用伺服估计型观察者控制控制电流数据的输出定时。 从磁盘的伺服扇区读取伺服信息，进行解码，并用于计算控制电流数据。 在以下伺服扇区的伺服信息完全解码之前，从先前读取的伺服扇区计算的控制电流数据被输出，转换成电流，并发送到磁头的致动器。
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