公开(公告)号：US08421527B2

公开(公告)日：2013-04-16

申请号：US13562157

申请日：2012-07-30

申请人： Toshio Sasaki ,  Kazuki Fukuoka ,  Ryo Mori ,  Yoshihiko Yasu

发明人： Toshio Sasaki ,  Kazuki Fukuoka ,  Ryo Mori ,  Yoshihiko Yasu

IPC分类号： G05F1/10

CPC分类号： H03K19/0016 ,  G06F1/3203 ,  G06F1/3287 ,  H01L27/0207 ,  H01L27/088 ,  H01L2224/48091 ,  H01L2924/13091 ,  Y02D10/171 ,  Y02D50/20 ,  H01L2924/00014 ,  H01L2924/00

摘要： The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

摘要翻译： 本发明旨在在低功耗结构中大幅度地提高电路布局面积的同时执行精细的低电压控制。 在将区域移动到低速模式的情况下，系统控制器分别向功率开关控制器和低功率驱动电路输出请求信号和使能信号，以关闭电源开关并执行 控制使得虚拟参考电位的电压电平变为约0.2V至约0.3V。 该区域在电源电压和虚拟参考电位之间的电压下工作，使得其在低速模式下被控制。

公开(公告)号：US08379425B2

公开(公告)日：2013-02-19

申请号：US12714309

申请日：2010-02-26

申请人： Kazuki Fukuoka ,  Yasuto Igarashi ,  Ryo Mori ,  Yoshihiko Yasu ,  Toshio Sasaki

发明人： Kazuki Fukuoka ,  Yasuto Igarashi ,  Ryo Mori ,  Yoshihiko Yasu ,  Toshio Sasaki

IPC分类号： H02M1/00 ,  G06F1/26

CPC分类号： H03K5/00 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/0928 ,  H01L27/11807 ,  H03K3/00 ,  H03K19/0016

摘要： Efficient reduction in power consumption is achieved by combinational implementation of a power cutoff circuit technique using power supply switch control and a DVFS technique for low power consumption. A power supply switch section fed with power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in a DEEP-NWELL region formed over a semiconductor substrate. Another power supply switch section fed with another power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in another DEEP-NWELL region formed over the semiconductor substrate. In this arrangement, there arises no possibility of short-circuiting between different power supplies via each DEEP-NWELL region formed over the semiconductor substrate.

摘要翻译： 通过使用电源开关控制和DVFS技术组合实现断电电路技术实现功耗的有效降低，实现低功耗。 在半导体基板上形成的DEEP-NWELL区域中，形成供给电源电压的电源开关部，由电源开关部进行电源切断的电路块和电平移位器。 供给另一电源电压的另一个电源开关部分，由电源开关部分执行电源切断的电路块和电平移位器形成在形成在半导体衬底上的另一个DEEP-NWELL区域中。 在这种布置中，不存在通过半导体衬底上形成的每个DEEP-NWELL区域在不同电源之间短路的可能性。

公开(公告)号：US08044709B2

公开(公告)日：2011-10-25

申请号：US12608105

申请日：2009-10-29

申请人： Toshio Sasaki ,  Kazuki Fukuoka ,  Ryo Mori ,  Yoshihiko Yasu

发明人： Toshio Sasaki ,  Kazuki Fukuoka ,  Ryo Mori ,  Yoshihiko Yasu

IPC分类号： G05F1/10

CPC分类号： H03K19/0016 ,  G06F1/3203 ,  G06F1/3287 ,  H01L27/0207 ,  H01L27/088 ,  H01L2224/48091 ,  H01L2924/13091 ,  Y02D10/171 ,  Y02D50/20 ,  H01L2924/00014 ,  H01L2924/00

摘要： The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

摘要翻译： 本发明旨在在低功耗结构中大幅度地提高电路布局面积的同时执行精细的低电压控制。 在将区域移动到低速模式的情况下，系统控制器分别向功率开关控制器和低功率驱动电路输出请求信号和使能信号，以关闭电源开关并执行 控制使得虚拟参考电位的电压电平变为约0.2V至约0.3V。 该区域在电源电压和虚拟参考电位之间的电压下工作，使得其在低速模式下被控制。

公开(公告)号：US08253481B2

公开(公告)日：2012-08-28

申请号：US13244553

申请日：2011-09-25

申请人： Toshio Sasaki ,  Kazuki Fukuoka ,  Ryo Mori ,  Yoshihiko Yasu

发明人： Toshio Sasaki ,  Kazuki Fukuoka ,  Ryo Mori ,  Yoshihiko Yasu

IPC分类号： G05F1/10

CPC分类号： H03K19/0016 ,  G06F1/3203 ,  G06F1/3287 ,  H01L27/0207 ,  H01L27/088 ,  H01L2224/48091 ,  H01L2924/13091 ,  Y02D10/171 ,  Y02D50/20 ,  H01L2924/00014 ,  H01L2924/00

摘要： The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

摘要翻译： 本发明旨在在低功耗结构中大幅度地提高电路布局面积的同时执行精细的低电压控制。 在将区域移动到低速模式的情况下，系统控制器分别向功率开关控制器和低功率驱动电路输出请求信号和使能信号，以关闭电源开关并执行 控制使得虚拟参考电位的电压电平变为约0.2V至约0.3V。 该区域在电源电压和虚拟参考电位之间的电压下工作，使得其在低速模式下被控制。

公开(公告)号：US20100219800A1

公开(公告)日：2010-09-02

申请号：US12714309

申请日：2010-02-26

申请人： Kazuki FUKUOKA ,  Yasuto Igarashi ,  Ryo Mori ,  Yoshihiko Yasu ,  Toshio Sasaki

发明人： Kazuki FUKUOKA ,  Yasuto Igarashi ,  Ryo Mori ,  Yoshihiko Yasu ,  Toshio Sasaki

IPC分类号： G05F1/10

CPC分类号： H03K5/00 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/0928 ,  H01L27/11807 ,  H03K3/00 ,  H03K19/0016

摘要： Efficient reduction in power consumption is achieved by combinational implementation of a power cutoff circuit technique using power supply switch control and a DVFS technique for low power consumption. A power supply switch section fed with power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in a DEEP-NWELL region formed over a semiconductor substrate. Another power supply switch section fed with another power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in another DEEP-NWELL region formed over the semiconductor substrate. In this arrangement, there arises no possibility of short-circuiting between different power supplies via each DEEP-NWELL region formed over the semiconductor substrate.

摘要翻译： 通过使用电源开关控制和DVFS技术组合实现断电电路技术实现功耗的有效降低，实现低功耗。 在半导体基板上形成的DEEP-NWELL区域中，形成供给电源电压的电源开关部，由电源开关部进行电源切断的电路块和电平移位器。 供给另一电源电压的另一个电源开关部分，由电源开关部分执行电源切断的电路块和电平移位器形成在形成在半导体衬底上的另一个DEEP-NWELL区域中。 在这种布置中，不存在通过半导体衬底上形成的每个DEEP-NWELL区域在不同电源之间短路的可能性。

公开(公告)号：US08400806B2

公开(公告)日：2013-03-19

申请号：US12972238

申请日：2010-12-17

申请人： Toshio Sasaki ,  Yoshihiko Yasu ,  Takashi Kuraishi ,  Ryo Mori

发明人： Toshio Sasaki ,  Yoshihiko Yasu ,  Takashi Kuraishi ,  Ryo Mori

IPC分类号： G11C5/02

CPC分类号： G11C5/145 ,  G11C5/025 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/49 ,  H01L2924/01015 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this power supply can be interrupted with respect to each of the divided functional blocks. The core region formed in the semiconductor chip is divided into multiple functional blocks. A power switch row in which multiple power switches are arranged is disposed in the boundaries between the divided functional blocks. These power switches have a function of controlling the supply of reference potential to each of functional blocks and the interruption of this supply. A feature of the invention is that reference pads are disposed directly above the power switch rows. This shortens the wires coupling together the reference pads and the power switches.

公开(公告)号：US20070215952A1

公开(公告)日：2007-09-20

申请号：US11614619

申请日：2006-12-21

申请人： Osamu OZAWA ,  Toshio Sasaki ,  Ryo Mori ,  Takashi Kuraishi ,  Yoshihiko Yasu ,  Koichiro Ishibashi

发明人： Osamu OZAWA ,  Toshio Sasaki ,  Ryo Mori ,  Takashi Kuraishi ,  Yoshihiko Yasu ,  Koichiro Ishibashi

IPC分类号： H01L29/76

CPC分类号： H01L27/1203 ,  H01L21/823857

摘要： The semiconductor integrated circuit has so-called SOI type first MOS transistors (MNtk, MPtk) and second MOS transistors (MNtn, MPtn). The first MOS transistors have a gate isolation film thicker than that the second MOS transistors have. The first and second MOS transistors constitute a power-supply-interruptible circuit (6) and a power-supply-uninterrupted circuit (7). The power-supply-interruptible circuit has the first MOS transistors each constituting a power switch (10) between a source line (VDD) and a ground line (VSS), and the second MOS transistors connected in series with the power switch. A gate control signal for the first MOS transistors each constituting a power switch is made larger in amplitude than that for the second MOS transistors. This enables power-source cutoff control with a high degree of flexibility commensurate with the device isolation structure, which an SOI type semiconductor integrated circuit has originally.

摘要翻译： 半导体集成电路具有所谓的SOI型第一MOS晶体管（MNtk，MPtk）和第二MOS晶体管（MNtn，MPtn）。 第一MOS晶体管具有比第二MOS晶体管更厚的栅极隔离膜。 第一和第二MOS晶体管构成电源可中断电路（6）和电源不间断电路（7）。 电源中断电路具有构成源极线（VDD）和接地线（VSS）之间的电源开关（10）的第一MOS晶体管，以及与电源开关串联连接的第二MOS晶体管。 构成功率开关的第一MOS晶体管的栅极控制信号的幅度比第二MOS晶体管的幅度大。 这使得能够实现与SOI原理的SOI型半导体集成电路的器件隔离结构相当的高度灵活性的电源切断控制。

公开(公告)号：US20100090282A1

公开(公告)日：2010-04-15

申请号：US12639996

申请日：2009-12-17

申请人： OSAMU OZAWA ,  Toshio Sasaki ,  Ryo Mori ,  Takashi Kuraishi ,  Yoshihiko Yasu ,  Koichiro Ishibashi

发明人： OSAMU OZAWA ,  Toshio Sasaki ,  Ryo Mori ,  Takashi Kuraishi ,  Yoshihiko Yasu ,  Koichiro Ishibashi

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/823857

摘要： The semiconductor integrated circuit has so-called SOI type first MOS transistors (MNtk, MPtk) and second MOS transistors (MNtn, MPtn). The first MOS transistors have a gate isolation film thicker than that the second MOS transistors have. The first and second MOS transistors constitute a power-supply-interruptible circuit (6) and a power-supply-uninterrupted circuit (7). The power-supply-interruptible circuit has the first MOS transistors each constituting a power switch (10) between a source line (VDD) and a ground line (VSS), and the second MOS transistors connected in series with the power switch. A gate control signal for the first MOS transistors each constituting a power switch is made larger in amplitude than that for the second MOS transistors. This enables power-source cutoff control with a high degree of flexibility commensurate with the device isolation structure, which an SOI type semiconductor integrated circuit has originally.

摘要翻译： 半导体集成电路具有所谓的SOI型第一MOS晶体管（MNtk，MPtk）和第二MOS晶体管（MNtn，MPtn）。 第一MOS晶体管具有比第二MOS晶体管更厚的栅极隔离膜。 第一和第二MOS晶体管构成电源可中断电路（6）和电源不间断电路（7）。 电源中断电路具有构成源极线（VDD）和接地线（VSS）之间的电源开关（10）的第一MOS晶体管，以及与电源开关串联连接的第二MOS晶体管。 构成功率开关的第一MOS晶体管的栅极控制信号的幅度比第二MOS晶体管的幅度大。 这使得能够实现与SOI原理的SOI型半导体集成电路的器件隔离结构相当的高度灵活性的电源切断控制。

公开(公告)号：US07623364B2

公开(公告)日：2009-11-24

申请号：US12016201

申请日：2008-01-17

申请人： Toshio Sasaki ,  Yoshihiko Yasu ,  Takashi Kuraishi ,  Ryo Mori

发明人： Toshio Sasaki ,  Yoshihiko Yasu ,  Takashi Kuraishi ,  Ryo Mori

IPC分类号： G11C5/02

CPC分类号： G11C5/145 ,  G11C5/025 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/49 ,  H01L2924/01015 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this power supply can be interrupted with respect to each of the divided functional blocks. The core region formed in the semiconductor chip is divided into multiple functional blocks. A power switch row in which multiple power switches are arranged is disposed in the boundaries between the divided functional blocks. These power switches have a function of controlling the supply of reference potential to each of functional blocks and the interruption of this supply. A feature of the invention is that reference pads are disposed directly above the power switch rows. This shortens the wires coupling together the reference pads and the power switches.

摘要翻译： 提供了一种能够减少用于操作形成在半导体器件的芯区域中的电路的工作电压的波动的技术。 该半导体器件被布置成使得芯区域被分成多个功能块并且可以提供电力，并且该电源可以相对于每个分割的功能块被中断。 形成在半导体芯片中的芯区域被分成多个功能块。 配置有多个功率开关的电源开关列设置在分割的功能块之间的边界。 这些电源开关具有控制每个功能块的参考电位供应和该电源的中断的功能。 本发明的特征在于，参考焊盘直接设置在功率开关行的正上方。 这会缩短将参考焊盘和电源开关连接在一起的电线。

公开(公告)号：US20090079465A1

公开(公告)日：2009-03-26

申请号：US11912272

申请日：2005-04-21

申请人： Toshio Sasaki ,  Yoshihiko Yasu ,  Ryo Mori ,  Koichiro Ishibashi ,  Yusuke Kanno

发明人： Toshio Sasaki ,  Yoshihiko Yasu ,  Ryo Mori ,  Koichiro Ishibashi ,  Yusuke Kanno

IPC分类号： H03K17/16

CPC分类号： H01L27/0207 ,  H01L27/11803

摘要： The present invention aims to make each power shutdown area appropriate.Cell areas each comprising a plurality of core cells arranged therein, and power switches disposed corresponding to the respective cell areas are provided. A plurality of power shutdown areas are respectively formed in units of the core cells. In each power shutdown area, power shutdown is enabled by the power switches corresponding to the power shutdown areas. Thus, the power shutdown areas can be set finely in the core cell units, and the appropriateness of each power shutdown area is achieved. With its appropriateness, a reduction in current consumption at standby is achieved.

摘要翻译： 本发明旨在使每个功率关闭区域适合。 提供了各自包括布置在其中的多个核心单元的单元区域，以及对应于各个单元区域布置的功率开关。 多个功率关闭区分别以核心单元为单位形成。 在每个电源关闭区域，通过与电源关闭区域对应的电源开关使能电源关闭。 因此，可以在核心单元单元中精细地设置功率关闭区域，并且实现每个功率关闭区域的适当性。 在适当的情况下，实现了待机状态下电流消耗的减少。