摘要:
A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or −1 arithmetic operation are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.
摘要:
A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.
摘要:
A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.
摘要:
A dynamic RAM includes sense amplifiers each formed of a latch circuit consisting of MOSFETs of a first and second conductivity types with the application of a first and second voltages to the sources thereof, respectively, and having a pair of input/output nodes corresponding to a first bit line pair which is connected with a number of dynamic memory cells, and further includes pairs of switching MOSFETs of the first conductivity type which connect selectively an input/output node pair of the latch circuits to a pair of second bit lines provided commonly to a plurality of the first bit line pair in response to the reception of the select signal. The switching MOSFETs have their threshold voltage set smaller in terms of absolute value than the threshold voltage of the MOSFETs of the first conductivity type of the latch circuits, and the select signal has its level of turning off the switching MOSFETs set greater in terms of absolute value than the first voltage with respect to the second voltage.
摘要:
A dynamic RAM includes sense amplifiers each formed of a latch circuit consisting of MOSFETs of a first and second conductivity types with the application of a first and second voltages to the sources thereof, respectively, and having a pair of input/output nodes corresponding to a first bit line pair which is connected with a number of dynamic memory cells, and further includes pairs of switching MOSFETs of the first conductivity type which connect selectively an input/output node pair of the latch circuits to a pair of second bit lines provided commonly to a plurality of the first bit line pair in response to the reception of the select signal. The switching MOSFETs have their threshold voltage set smaller in terms of absolute value than the threshold voltage of the MOSFETs of the first conductivity type of the latch circuits, and the select signal has its level of turning off the switching MOSFETs set greater in terms of absolute value than the first voltage with respect to the second voltage.
摘要:
According to one embodiment, an X-ray computed tomography apparatus includes an X-ray tube, an X-ray detector, and a rotating unit. The first reconstruction processing reconstructs a clinical image based on projection data detected by the X-ray detector. The second reconstruction processing reconstructs a noise image based on noise data. The clinical image is combined with the noise image.
摘要:
A low-temperature plasma treatment is applied to a surface of an aramid paper so as to allow the surface to have a compositional atomic ratio X (O/C) of the number of oxygen atoms (O) to the number of carbon atoms (C) ranging from 110% to 220% of a theoretical atomic ratio. The treatment is performed at an intensity ranging from 120 to 1500 W·min/m2 with a low-temperature plasma treatment apparatus of internal electrode system. The aramid paper is superposed with a nonhydrolyzable resin film and the resulting article is pressurized to give an aramid-resin film laminate. The laminate is inexpensive, has both superior electrical properties and high mechanical strength, excels in elasticity, and is useful as an insulation material.
摘要翻译:将低温等离子体处理施加到芳族聚酰胺纸的表面,以使表面具有氧原子数(O)与碳原子数(C)的组成原子比X(O / C) )为理论原子比的110%至220%。 用内部电极系统的低温等离子体处理装置,以120〜1500W·min / m 2的强度进行处理。 将芳族聚酰胺纸与不可水解的树脂膜重叠,并将所得制品加压,得到芳族聚酰胺树脂膜层压体。 该层压板是廉价的,具有优异的电性能和高机械强度,弹性优异,并且可用作绝缘材料。
摘要:
An eyelid detection device that, based on first order differential values and second order differential values of vertical density change at an eyelid boundary in an eye image, shifts the second order differential values upwards by ¼ of the cycle of density change frequency of an eyelid boundary and combines the first order differential values and the second order differential values to compute upper eyelid feature amounts. The eyelid detection device detects a boundary between an upper eyelid and eyeball based on peak points in the vertical direction of the computed upper eyelid feature amounts. Consequently, the boundary between an eyelid and eyeball can be accurately detected even when the eyelid has been applied with makeup.
摘要:
Detecting with good precision an eye inside corner position and an eye outside corner position as face feature points even when the eye inside corner and/or the eye outside corner portions are obscured by noise. First eyelid profile modeling is performed with a Bezier curve expressed by a fixed control point P3 indicating an eye inside corner first position detected in an image, a fixed control point P4 indicating an eye outside corner first position, a control point P1 corresponding to an upper eyelid position candidate (first parameter), and a control point P2 corresponding to a lower eyelid position candidate (second parameter). Then in a second eyelid profile model with fixed P1 and P2 of the first eyelid profile model having the highest fitting evaluation value λ to the eyelid profile in the image, the values of a control point P3 indicating an eye inside corner position candidate (third parameter) and a control point P4 indicating an eye outside corner candidate (fourth parameter) at a maximum of a fitting evaluation value λ when changing the values of the control point P3 and control point P4 are determined as an eye inside corner second position and an eye outside corner second position, respectively.
摘要:
A data processing device is provided enabling faster read access to data in an on-chip EEPROM with relative ease, without increasing the area occupied by the chip and its power consumption. The on-chip nonvolatile memory included in the data processing device is provided with a pre-read cache which latches all or part of data, once having been read to bit lines from an array of nonvolatile memory cells by selecting a row address, and a selecting circuit which selects a portion of the data latched by the pre-read cache by selecting a portion of columns. Control is performed to retain address information for data latched by the pre-read cache, inhibit latching new data into the pre-read cache for read access to data in the nonvolatile memory according to the same address as the retained address information, and cause the selecting circuit to select the data latched by the pre-read cache.