公开(公告)号：US08183616B2

公开(公告)日：2012-05-22

申请号：US12873668

申请日：2010-09-01

申请人： Tsuyoshi Fujiwara ,  Toshinori Imai ,  Takeshi Saikawa ,  Yoshinori Kawasaki ,  Mitsuhiro Toya ,  Shunji Mori ,  Yoshiyuki Okabe

发明人： Tsuyoshi Fujiwara ,  Toshinori Imai ,  Takeshi Saikawa ,  Yoshinori Kawasaki ,  Mitsuhiro Toya ,  Shunji Mori ,  Yoshiyuki Okabe

IPC分类号： H01L29/94

CPC分类号： H01L28/91 ,  H01L27/10852 ,  H01L28/87

摘要： Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode, another capacitor insulating film and an upper electrode. Since the intermediate electrode has a step difference, each of the distance between the intermediate electrode and lower electrode and the distance between the intermediate electrode and upper electrode in a region other than the capacitor formation region becomes greater than that in the capacitor formation region. For example, the lower electrode is brought into direct contact with the capacitor insulating film in the capacitor formation region, while the lower electrode is not brought into direct contact with the capacitor insulating film in the region other than the capacitor formation region.

摘要翻译： 提供了一种能够减小电容器的寄生电容同时减小电容器所占空间的技术。 通过在由下电极构成的电容器，电容绝缘膜和中间电极上形成电容器，由中间电极，另一电容绝缘膜和上电极构成的另一电容器形成堆叠结构。 由于中间电极具有台阶差，所以在电容器形成区域以外的区域中，中间电极和下部电极之间的距离以及中间电极与上部电极之间的距离变得比电容器形成区域的大。 例如，下电极与电容器形成区域中的电容绝缘膜直接接触，而在电容器形成区域以外的区域中，下电极不与电容器绝缘膜直接接触。

公开(公告)号：US20060289917A1

公开(公告)日：2006-12-28

申请号：US11473229

申请日：2006-06-23

申请人： Tsuyoshi Fujiwara ,  Toshinori Imai ,  Takeshi Saikawa ,  Yoshihiro Kawasaki ,  Mitsuhiro Toya ,  Shunji Mori ,  Yoshiyuki Okabe

发明人： Tsuyoshi Fujiwara ,  Toshinori Imai ,  Takeshi Saikawa ,  Yoshihiro Kawasaki ,  Mitsuhiro Toya ,  Shunji Mori ,  Yoshiyuki Okabe

IPC分类号： H01L29/94

CPC分类号： H01L28/91 ,  H01L27/10852 ,  H01L28/87

摘要： Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode, another capacitor insulating film and an upper electrode. Since the intermediate electrode has a step difference, each of the distance between the intermediate electrode and lower electrode and the distance between the intermediate electrode and upper electrode in a region other than the capacitor formation region becomes greater than that in the capacitor formation region. For example, the lower electrode is brought into direct contact with the capacitor insulating film in the capacitor formation region, while the lower electrode is not brought into direct contact with the capacitor insulating film in the region other than the capacitor formation region.

摘要翻译： 提供了一种能够减小电容器的寄生电容同时减小电容器所占空间的技术。 通过在由下电极构成的电容器，电容绝缘膜和中间电极上形成电容器，由中间电极，另一电容绝缘膜和上电极构成的另一电容器形成堆叠结构。 由于中间电极具有台阶差，所以在电容器形成区域以外的区域中，中间电极和下部电极之间的距离以及中间电极和上部电极之间的距离变得比电容器形成区域的大。 例如，下电极与电容器形成区域中的电容绝缘膜直接接触，而在电容器形成区域以外的区域中，下电极不与电容器绝缘膜直接接触。

公开(公告)号：US06746913B2

公开(公告)日：2004-06-08

申请号：US10083416

申请日：2002-02-27

申请人： Tsuyoshi Fujiwara ,  Takeshi Saikawa ,  Ryouichi Furukawa ,  Masato Kunitomo

发明人： Tsuyoshi Fujiwara ,  Takeshi Saikawa ,  Ryouichi Furukawa ,  Masato Kunitomo

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/31612 ,  H01L27/0629 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894

摘要： A silicon oxide film on which a capacitor of a semiconductor integrated circuit device is formed is formed by the plasma CVD method at a temperature of 450° C. to 700° C. In this semiconductor integrated circuit device, a memory cell formed of a MISFET for data transfer and a capacitor is formed in a memory cell forming area, and an n channel MISFET and a p channel MISFET constituting a logic circuit is formed in a logic circuit forming area. As a result, the amount of degassing from the silicon oxide film can be reduced. Therefore, the growth of silicon grains on a surface of the silicon film constituting a lower electrode of the capacitor is not hindered by the degassing, and it becomes possible to increase the capacitance. Also, the step of a heat treatment for removing the moisture and the like after forming the silicon oxide film can be omitted, and it becomes possible to prevent the deterioration of the property of the MISFET.

摘要翻译： 在其上形成有半导体集成电路器件的电容器的氧化硅膜通过等离子体CVD法在450℃至700℃的温度下形成。在该半导体集成电路器件中，由MISFET形成的存储单元 用于数据传送，并且在存储单元形成区域中形成电容器，并且在逻辑电路形成区域中形成构成逻辑电路的n沟道MISFET和ap沟道MISFET。 结果，可以减少从氧化硅膜脱气的量。 因此，构成电容器的下电极的硅膜的表面上的硅晶粒的生长不受脱气的阻碍，能够增加电容。 此外，可以省略在形成氧化硅膜之后除去水分等的步骤，并且可以防止MISFET的性能劣化。

公开(公告)号：US20070114631A1

公开(公告)日：2007-05-24

申请号：US11653321

申请日：2007-01-16

申请人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

发明人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

IPC分类号： H01L29/00

CPC分类号： H01L21/76224 ,  H01L27/0207 ,  H01L27/10894

摘要： A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patters in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited.

摘要翻译： 一种制造半导体集成电路器件的方法包括以下步骤：在半导体衬底的隔离区域中形成隔离沟槽，通过涂覆方法沉积的第一绝缘膜将隔离沟填充到其深度方向上的预定中间位置， 用第二绝缘膜填充绝缘沟槽的剩余深度部分，然后在半导体衬底上形成多个图案，在多个图案之间填充形成沟槽直到预定中间位置的沟槽 沟槽深度方向与通过涂覆方法沉积的第三绝缘膜，并且填充第三绝缘膜填充有比第三绝缘膜更难蚀刻的第四绝缘膜的沟槽的剩余部分。 该方法还可以包括在第一绝缘膜沉积之前在具有相对不同的平面尺寸的隔离区的相对大的隔离区域中形成伪图案的步骤。

公开(公告)号：US20050148155A1

公开(公告)日：2005-07-07

申请号：US11055745

申请日：2005-02-11

申请人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

发明人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

IPC分类号： H01L21/76 ,  G02B17/00 ,  G02B21/00 ,  G02B23/00 ,  H01L21/302 ,  H01L21/312 ,  H01L21/316 ,  H01L21/461 ,  H01L21/762 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L21/76229 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/3125 ,  H01L21/31612 ,  H01L27/0211 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10894

摘要： A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patterns in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited

摘要翻译： 一种制造半导体集成电路器件的方法包括以下步骤：在半导体衬底的隔离区域中形成隔离沟槽，通过涂覆方法沉积的第一绝缘膜将隔离沟填充到其深度方向上的预定中间位置， 用第二绝缘膜填充绝缘沟槽的剩余深度部分，然后在半导体衬底上形成多个图案，在多个图案之间填充形成沟槽直到预定中间位置的沟槽 沟槽深度方向与通过涂覆方法沉积的第三绝缘膜，并且填充第三绝缘膜填充有比第三绝缘膜更难蚀刻的第四绝缘膜的沟槽的剩余部分。 该方法还可以包括在第一绝缘膜沉积之前在具有相对不同的平面尺寸的隔离区的相对较大的隔离区域中形成虚拟图案的步骤

公开(公告)号：US06767782B2

公开(公告)日：2004-07-27

申请号：US10082311

申请日：2002-02-26

申请人： Takeshi Saikawa ,  Ryohei Maeno ,  Sadayuki Okudaira ,  Tetsuo Saito ,  Tsuyoshi Tamaru ,  Kazutoshi Ohmori

发明人： Takeshi Saikawa ,  Ryohei Maeno ,  Sadayuki Okudaira ,  Tetsuo Saito ,  Tsuyoshi Tamaru ,  Kazutoshi Ohmori

IPC分类号： H01L218238

CPC分类号： H01L21/76801 ,  H01L21/76819 ,  H01L21/76838 ,  H01L21/7684 ,  Y10S438/906

摘要： Charge-up damages to a substrate are reduced in a manufacturing process using plasma, and the reliability of a semiconductor device is improved. By forming an insulating film on the back of a substrate before a step of forming a first wiring layer, even if a plasma CVD method, a sputtering method, or a dry-etching method is used in a wiring-forming step executed later, then it is possible to suppress electric charges which are generated on the substrate and which flow to the ground potential through the substrate, and to prevent damages to the substrate due to charge-up.

摘要翻译： 在使用等离子体的制造工艺中，对基板的充电损坏减少，并且提高了半导体器件的可靠性。通过在形成第一布线层的步骤之前在基板背面形成绝缘膜，即使 在稍后执行的布线形成步骤中使用等离子体CVD法，溅射法或干蚀刻法，则可以抑制在基板上产生的电荷，并且通过基板流向接地电位， 并防止由于充电而损坏基板。

公开(公告)号：US07208391B2

公开(公告)日：2007-04-24

申请号：US11149538

申请日：2005-06-10

申请人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

发明人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

IPC分类号： H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/3125 ,  H01L21/31612 ,  H01L27/0211 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10894

摘要： A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patters in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited.

摘要翻译： 一种制造半导体集成电路器件的方法包括以下步骤：在半导体衬底的隔离区域中形成隔离沟槽，通过涂覆方法沉积的第一绝缘膜将隔离沟填充到其深度方向上的预定中间位置， 用第二绝缘膜填充绝缘沟槽的剩余深度部分，然后在半导体衬底上形成多个图案，在多个图案之间填充形成沟槽直到预定中间位置的沟槽 沟槽深度方向与通过涂覆方法沉积的第三绝缘膜，并且填充第三绝缘膜填充有比第三绝缘膜更难蚀刻的第四绝缘膜的沟槽的剩余部分。 该方法还可以包括在第一绝缘膜沉积之前在具有相对不同的平面尺寸的隔离区的相对大的隔离区域中形成伪图案的步骤。

公开(公告)号：US20050239257A1

公开(公告)日：2005-10-27

申请号：US11149538

申请日：2005-06-10

申请人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

发明人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

IPC分类号： H01L21/76 ,  G02B17/00 ,  G02B21/00 ,  G02B23/00 ,  H01L21/302 ,  H01L21/312 ,  H01L21/316 ,  H01L21/461 ,  H01L21/762 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L21/76229 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/3125 ,  H01L21/31612 ,  H01L27/0211 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10894

摘要： A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patters in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited.

公开(公告)号：US07074691B2

公开(公告)日：2006-07-11

申请号：US11149539

申请日：2005-06-10

申请人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

发明人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

IPC分类号： H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/3125 ,  H01L21/31612 ,  H01L27/0211 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10894

摘要： A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patters in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited.

摘要翻译： 一种制造半导体集成电路器件的方法包括以下步骤：在半导体衬底的隔离区域中形成隔离沟槽，通过涂覆方法沉积的第一绝缘膜将隔离沟填充到其深度方向上的预定中间位置， 用第二绝缘膜填充绝缘沟槽的剩余深度部分，然后在半导体衬底上形成多个图案，在多个图案之间填充形成沟槽直到预定中间位置的沟槽 沟槽深度方向与通过涂覆方法沉积的第三绝缘膜，并且填充第三绝缘膜填充有比第三绝缘膜更难蚀刻的第四绝缘膜的沟槽的剩余部分。 该方法还可以包括在第一绝缘膜沉积之前在具有相对不同的平面尺寸的隔离区的相对大的隔离区域中形成伪图案的步骤。

公开(公告)号：US07060589B2

公开(公告)日：2006-06-13

申请号：US11055745

申请日：2005-02-11

申请人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

发明人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

IPC分类号： H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/3125 ,  H01L21/31612 ,  H01L27/0211 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10894

摘要： A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patterns in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited

摘要翻译： 一种制造半导体集成电路器件的方法包括以下步骤：在半导体衬底的隔离区域中形成隔离沟槽，通过涂覆方法沉积的第一绝缘膜将隔离沟填充到其深度方向上的预定中间位置， 用第二绝缘膜填充绝缘沟槽的剩余深度部分，然后在半导体衬底上形成多个图案，在多个图案之间填充形成沟槽直到预定中间位置的沟槽 沟槽深度方向与通过涂覆方法沉积的第三绝缘膜，并且填充第三绝缘膜填充有比第三绝缘膜更难蚀刻的第四绝缘膜的沟槽的剩余部分。 该方法还可以包括在第一绝缘膜沉积之前在具有相对不同的平面尺寸的隔离区的相对较大的隔离区域中形成虚拟图案的步骤