ADJUSTABLE LABYRINTH SEAL
    1.
    发明申请
    ADJUSTABLE LABYRINTH SEAL 有权
    可调节的乳胶密封

    公开(公告)号:US20150132126A1

    公开(公告)日:2015-05-14

    申请号:US14487168

    申请日:2014-09-16

    Abstract: An adjustable seal and method for varying a radial distance between the adjustable seal and a rotor of a turbomachine are provided. The adjustable seal may include a first annular member defining a plurality of radial channels, and a second annular member defining a plurality of slots at least partially extending therethrough. The second annular member may be concentric with the first annular member and configured to rotate relative to the first annular member. The adjustable seal may also include a plurality of seal segments interposed between the first annular member and the second annular member. Each seal segment of the plurality of seal segments may be slidably disposed in a respective radial channel of the plurality of radial channels and may have an axial projection slidably disposed in a respective slot of the plurality of slots.

    Abstract translation: 提供了用于改变可调节密封件和涡轮机的转子之间的径向距离的可调节密封件和方法。 可调节密封件可以包括限定多个径向通道的第一环形构件,以及限定至少部分延伸穿过其中的多个槽的第二环形构件。 第二环形构件可以与第一环形构件同心并且构造成相对于第一环形构件旋转。 可调节密封件还可以包括插入在第一环形构件和第二环形构件之间的多个密封段。 多个密封段的每个密封段可以可滑动地设置在多个径向通道的相应的径向通道中,并且可以具有可滑动地设置在多个狭槽的相应狭槽中的轴向突出部。

    Duration minimum and maximum circuit for performance counter
    2.
    发明授权
    Duration minimum and maximum circuit for performance counter 失效
    性能计数器的持续时间最小和最大电路

    公开(公告)号:US07676530B2

    公开(公告)日:2010-03-09

    申请号:US11021259

    申请日:2004-12-23

    CPC classification number: G06F11/348 G06F2201/88

    Abstract: A circuit for tracking the minimum and maximum duration of an event of interest is described. The circuit is connected to a counter for counting a number of clock cycles that the event of interest is active and comprises logic for detecting deactivation of the event of interest and generating a duration end signal; logic responsive to the duration end signal for comparing a count value with a shadow value; and logic for updating the shadow value based on results of the comparing.

    Abstract translation: 描述用于跟踪感兴趣事件的最小和最大持续时间的电路。 电路连接到计数器,用于计数感兴趣事件处于活动状态的多个时钟周期,并且包括用于检测感兴趣事件的去激活并产生持续时间结束信号的逻辑; 响应于持续时间结束信号的逻辑,用于将计数值与阴影值进行比较; 以及基于比较结果来更新阴影值的逻辑。

    System and method to qualify data capture
    3.
    发明申请
    System and method to qualify data capture 有权
    系统和方法来限定数据捕获

    公开(公告)号:US20060156290A1

    公开(公告)日:2006-07-13

    申请号:US11033226

    申请日:2005-01-11

    CPC classification number: G06F11/348

    Abstract: One disclosed embodiment may comprise a system that includes a qualification system that qualifies data on an associated bus for capture and provides a qualification signal as a function of at least one signal that describes a characteristic of the data on the associated bus. A data capture system stores qualified data from the associated bus based on the qualification signal and a trigger signal, the trigger signal defining a capture session.

    Abstract translation: 一个公开的实施例可以包括系统,该系统包括限定相关总线上的数据进行捕获的鉴定系统,并且提供作为描述相关总线上的数据的特性的至少一个信号的函数的限定信号。 数据采集​​系统基于鉴定信号和触发信号存储来自关联总线的合格数据,触发信号定义捕获会话。

    Duration minimum and maximum circuit for performance counter
    4.
    发明申请
    Duration minimum and maximum circuit for performance counter 失效
    性能计数器的持续时间最小和最大电路

    公开(公告)号:US20050283677A1

    公开(公告)日:2005-12-22

    申请号:US11021259

    申请日:2004-12-23

    CPC classification number: G06F11/348 G06F2201/88

    Abstract: A circuit for tracking the minimum and maximum duration of an event of interest is described. The circuit is connected to a counter for counting a number of clock cycles that the event of interest is active and comprises logic for detecting deactivation of the event of interest and generating a duration end signal; logic responsive to the duration end signal for comparing a count value with a shadow value; and logic for updating the shadow value based on results of the comparing.

    Abstract translation: 描述用于跟踪感兴趣事件的最小和最大持续时间的电路。 电路连接到计数器,用于计数感兴趣事件处于活动状态的多个时钟周期,并且包括用于检测感兴趣事件的去激活并产生持续时间结束信号的逻辑; 响应于持续时间结束信号的逻辑,用于将计数值与阴影值进行比较; 以及基于比较结果来更新阴影值的逻辑。

    Edge detect circuit for performance counter
    5.
    发明申请
    Edge detect circuit for performance counter 审中-公开
    性能计数器的边缘检测电路

    公开(公告)号:US20050283669A1

    公开(公告)日:2005-12-22

    申请号:US11022021

    申请日:2004-12-23

    CPC classification number: G06F11/348 G06F11/3466 G06F2201/88

    Abstract: An edge detect circuit connected to a bus carrying data is described. In one embodiment, the edge detect circuit comprises logic for detecting an edge of a raw increment signal and logic for activating an increment signal upon detection of an edge of the raw increment signal.

    Abstract translation: 描述了连接到总线承载数据的边缘检测电路。 在一个实施例中,边缘检测电路包括用于检测原始增量信号的边缘的逻辑和用于在检测到原始增量信号的边缘时激活增量信号的逻辑。

    DYNAMIC ALLOCATION OF VIDEO RESOURCES
    6.
    发明申请
    DYNAMIC ALLOCATION OF VIDEO RESOURCES 有权
    视频资源的动态分配

    公开(公告)号:US20130265432A1

    公开(公告)日:2013-10-10

    申请号:US13443377

    申请日:2012-04-10

    CPC classification number: H04N7/181 G06Q20/1085 G07F19/211 H04N7/147

    Abstract: Video transaction machines (VTMs) facilitate communications and transactions between customers of a financial institution and video transaction resources, such as video agents, by establishing a video session between a VTM and a video agent workstation. After a computing device of the financial institution receives information identifying the customer, VTM, or VTM location requesting the services of a video agent, the computing device may place the customer in one or more virtual queues based on an overall visit time at the VTM location. In order to maintain a visit time at the VTM location below a predetermined visit time threshold, the controller may prioritize transactions at VTMs with longer visit times over transactions at VTMs with shorter visit times.

    Abstract translation: 视频交易机(VTM)通过在VTM和视频代理工作站之间建立视频会话来促进金融机构的客户和视频交易资源(例如视频代理)之间的通信和交易。 在金融机构的计算设备接收到识别要求视频代理服务的客户,VTM或VTM位置的信息之后,计算设备可以基于在VTM位置处的总访问时间将客户置于一个或多个虚拟队列中 。 为了将VTM位置的访问时间保持在预定的访问时间阈值以下,控制器可以以比较短的访问时间的VTM的事务具有较长访问时间的VTM优先处理事务。

    System and method to control data capture
    7.
    发明申请
    System and method to control data capture 有权
    控制数据采集的系统和方法

    公开(公告)号:US20060156102A1

    公开(公告)日:2006-07-13

    申请号:US11032928

    申请日:2005-01-11

    CPC classification number: G01R31/3177

    Abstract: One disclosed embodiment may comprise a system that includes a data capture system that stores a set of data from an associated data source in response to a store signal while enabled based on a control signal. A control system provides the control signal based on a number of store cycles relative to an event to define the set of data, the number of store cycles varying based on the store signal.

    Abstract translation: 一个公开的实施例可以包括一种系统,该系统包括数据捕获系统,其基于控制信号在启用时响应于存储信号存储来自相关联的数据源的数据集。 控制系统基于相对于事件的存储周期数来提供控制信号,以定义数据集合,存储循环的数量基于存储信号而变化。

    General purpose delay logic
    8.
    发明申请
    General purpose delay logic 失效
    通用延时逻辑

    公开(公告)号:US20050278675A1

    公开(公告)日:2005-12-15

    申请号:US11207635

    申请日:2005-08-19

    Applicant: Tyler Johnson

    Inventor: Tyler Johnson

    CPC classification number: H03K5/135 G01R31/3016 G01R31/31727

    Abstract: A logic circuit for delaying a signal input thereto by a number of clock cycles X is described. In one embodiment, the logic circuit comprises a demultiplexer (“DEMUX”) which includes an input for receiving the signal and N outputs; a register array comprising at least X registers, wherein each of the N outputs of the DEMUX is connected to a corresponding one of the X registers; and a multiplexer (“MUX”) comprising M inputs, wherein each of the M inputs is connected to one of the registers.

    Abstract translation: 描述用于将输入到其的信号延迟多个时钟周期X的逻辑电路。 在一个实施例中,逻辑电路包括解复用器(“DEMUX”),其包括用于接收信号和N个输出的输入; 包括至少X个寄存器的寄存器阵列,其中DEMUX的N个输出中的每一个连接到X个寄存器中的相应一个; 以及包括M个输入的多路复用器(“MUX”),其中M个输入中的每一个连接到一个寄存器。

    Performance monitoring system
    9.
    发明申请
    Performance monitoring system 有权
    绩效监测系统

    公开(公告)号:US20050273671A1

    公开(公告)日:2005-12-08

    申请号:US11022079

    申请日:2004-12-23

    CPC classification number: G06F11/348 G06F2201/88

    Abstract: A system for validating data collected in a first clock domain. A performance counter is disposed in a second clock domain to perform performance computations relative to the data. Validation circuitry is in communication with the data in order to provide to the performance counter a validation signal indicative of the validity of the data.

    Abstract translation: 用于验证在第一时钟域中收集的数据的系统。 性能计数器被布置在第二时钟域中以相对于数据执行性能计算。 验证电路与数据通信,以向性能计数器提供指示数据有效性的验证信号。

Patent Agency Ranking