公开(公告)号：US20170316830A1

公开(公告)日：2017-11-02

申请号：US15638352

申请日：2017-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao Su ,  Chow Yee Lim ,  CHAO JIANG ,  Hong Liao

IPC: G11C16/04 ,  H01L27/11521 ,  H01L23/528 ,  H01L23/522 ,  H01L21/28 ,  H01L29/51 ,  H01L21/268

CPC classification number: H01L23/5226 ,  G11C16/0433 ,  H01L21/2686 ,  H01L21/28273 ,  H01L23/528 ,  H01L27/11521 ,  H01L29/518

Abstract: A light-erasable embedded memory device and a method for manufacturing the same are provided in the present invention. The light-erasable embedded memory device includes a substrate with a memory region and a core circuit region, a floating gate on the memory region of the substrate, at least two light-absorbing films above the floating gate, wherein each light-absorbing film is provided with at least one dummy via hole overlapping the floating gate, and a dielectric layer on each light-absorbing film and filling up the dummy via holes.

公开(公告)号：US20230025163A1

公开(公告)日：2023-01-26

申请号：US17404939

申请日：2021-08-17

Applicant: United Microelectronics Corp.

Inventor： Wen Wen Gong ,  Xiaofei Han ,  Chow Yee Lim ,  Hong Liao ,  Jun Qian

IPC: H01L21/308 ,  H01L27/11556

Abstract: A method of manufacturing a semiconductor structure including the following steps is provided. A substrate is provided. The substrate has a first region and a second region. A stacked structure is formed on the substrate in the first region. The stacked structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, a first conductive layer, and a first hard mask layer. A dielectric material layer is formed on the substrate in the second region. A second conductive layer is formed on the dielectric material layer in the second region. A first patterned photoresist layer is formed. The first hard mask layer exposed by the first patterned photoresist layer and a portion of the dielectric material layer exposed by the first patterned photoresist layer are removed by using the first patterned photoresist layer as a mask.

公开(公告)号：US09911847B1

公开(公告)日：2018-03-06

申请号：US15647286

申请日：2017-07-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hock Chun Chin ,  Lanxiang Wang ,  Hong Liao ,  Chao Jiang ,  Chow Yee Lim

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/78391 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28291 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/7881 ,  H01L29/792

Abstract: A non-volatile memory device includes a substrate, a gate stack structure, an erase gate structure, and a ferroelectric layer. The gate stack structure is disposed on the substrate. The erase gate structure is disposed on the substrate and disposed at a first side of the gate stack structure. The ferroelectric layer is disposed on a sidewall of the gate stack structure, and the ferroelectric layer is disposed between the gate stack structure and the erase gate structure. The ferroelectric layer disposed between the gate stack structure and the erase gate structure may be used to forma negative capacitance effect for amplifying the voltage applied to the erase gate structure. The purpose of reducing power consumption may be achieved accordingly.

公开(公告)号：US20180342394A1

公开(公告)日：2018-11-29

申请号：US15603465

申请日：2017-05-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi Qiang Mu ,  Chow Yee Lim ,  Hui Yang ,  YONG BIN FAN ,  JIANJUN YANG ,  Chih-Chien Chang

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/49 ,  H01L29/51

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first polysilicon layer is formed on a substrate. A planarization process to the first polysilicon layer is performed. A first etching back process to the first polysilicon layer is performed after the planarization process. A second etching back process to the first polysilicon layer is performed after the first etching back process. A first wet clean process to the first polysilicon layer is performed after the first etching back process and before the second etching back process.

公开(公告)号：US10141194B1

公开(公告)日：2018-11-27

申请号：US15603465

申请日：2017-05-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi Qiang Mu ,  Chow Yee Lim ,  Hui Yang ,  Yong Bin Fan ,  Jianjun Yang ,  Chih-Chien Chang

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/28273 ,  H01L21/02071 ,  H01L21/02074 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first polysilicon layer is formed on a substrate. A planarization process to the first polysilicon layer is performed. A first etching back process to the first polysilicon layer is performed after the planarization process. A second etching back process to the first polysilicon layer is performed after the first etching back process. A first wet clean process to the first polysilicon layer is performed after the first etching back process and before the second etching back process.

公开(公告)号：US10079204B2

公开(公告)日：2018-09-18

申请号：US15638352

申请日：2017-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao Su ,  Chow Yee Lim ,  Chao Jiang ,  Hong Liao

IPC: H01L23/48 ,  H01L23/522 ,  H01L27/11521 ,  H01L29/51 ,  H01L21/28 ,  H01L21/268 ,  H01L23/528 ,  G11C16/04

CPC classification number: H01L23/5226 ,  G11C16/0433 ,  G11C16/18 ,  G11C17/143 ,  G11C2216/26 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11546 ,  H01L29/518

Abstract: A light-erasable embedded memory device and a method for manufacturing the same are provided in the present invention. The light-erasable embedded memory device includes a substrate with a memory region and a core circuit region, a floating gate on the memory region of the substrate, at least two light-absorbing films above the floating gate, wherein each light-absorbing film is provided with at least one dummy via hole overlapping the floating gate, and a dielectric layer on each light-absorbing film and filling up the dummy via holes.

公开(公告)号：US09728260B1

公开(公告)日：2017-08-08

申请号：US15140506

申请日：2016-04-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao Su ,  Chow Yee Lim ,  Chao Jiang ,  Hong Liao

IPC: H01L21/336 ,  G11C16/04 ,  H01L27/11521 ,  H01L29/51 ,  H01L21/28 ,  H01L21/268 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5226 ,  G11C16/0433 ,  H01L21/2686 ,  H01L21/28273 ,  H01L23/528 ,  H01L27/11521 ,  H01L29/518

Abstract: A light-erasable embedded memory device and a method for manufacturing the same are provided in the present invention. The light-erasable embedded memory device includes a substrate with a memory region and a core circuit region, a floating gate on the memory region of the substrate, at least one light-absorbing film above the floating gate, wherein at least one light-absorbing film is provided with dummy via holes overlapping the floating gate, and a dielectric layer on the light-absorbing film and filling up the dummy via holes.