公开(公告)号：US11990346B2

公开(公告)日：2024-05-21

申请号：US17391075

申请日：2021-08-02

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chuan-Chang Wu ,  Zhen Wu ,  Hsuan-Hsu Chen ,  Chun-Lung Chen

IPC分类号： H01L21/311 ,  H01L21/3213 ,  H01L29/66

CPC分类号： H01L21/32134 ,  H01L29/66545

摘要： A method for a clean procedure during manufacturing a semiconductor device, includes: providing a patterned sacrificial gate structure including a gate dielectric and a sacrificial layer; wherein the patterned sacrificial gate structure is embedded in a dielectric layer and an upper surface of the sacrificial layer is exposed; performing a first etching process to remove the sacrificial layer; and performing a hydrophilic treatment and a hydrophobic treatment to remove a residue of the sacrificial layer.

公开(公告)号：US20240016062A1

公开(公告)日：2024-01-11

申请号：US17874327

申请日：2022-07-27

申请人： United Microelectronics Corp.

发明人： Shun-Yu Huang ,  Yi-Wei Tseng ,  Chih-Wei Kuo ,  Yi-Xiang Chen ,  Hsuan-Hsu Chen ,  Chun-Lung Chen

IPC分类号： H01L43/12 ,  H01L27/22 ,  H01L43/02

CPC分类号： H01L43/12 ,  H01L27/222 ,  H01L43/02

摘要： A method of fabricating an MTJ device is provided including the following process. A first via is formed in the first dielectric layer. A first electrode layer is formed on the first dielectric layer and the first via. An MTJ stack layer is formed on the first electrode layer. A patterned second electrode layer is formed on the MTJ stack layer and used as a mask. A first ion beam etching process is performed to etch the patterned second electrode layer and pattern the MTJ stack layer and the first electrode layer to form a second electrode, an MTJ stack structure, and a first electrode. A first protective layer is formed to cover the second electrode and the MTJ stack structure. A second ion beam etching process is performed to remove a portion of the MTJ stack structure and a portion of the first electrode.

公开(公告)号：US20230320229A1

公开(公告)日：2023-10-05

申请号：US18195383

申请日：2023-05-10

申请人： UNITED MICROELECTRONICS CORP.

发明人： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC分类号： H10N50/10 ,  H01L21/768 ,  H01L21/762 ,  H10N50/80

CPC分类号： H10N50/10 ,  H01L21/762 ,  H01L21/76802 ,  H10N50/80 ,  H10N35/01

摘要： A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and form a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

公开(公告)号：US11778922B2

公开(公告)日：2023-10-03

申请号：US17533003

申请日：2021-11-22

申请人： UNITED MICROELECTRONICS CORP.

发明人： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC分类号： H01L41/47 ,  H10N50/10 ,  H01L21/768 ,  H01L21/762 ,  H10N50/80 ,  H10N35/01

CPC分类号： H10N50/10 ,  H01L21/762 ,  H01L21/76802 ,  H10N50/80 ,  H10N35/01

摘要： A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

公开(公告)号：US11527710B2

公开(公告)日：2022-12-13

申请号：US16529779

申请日：2019-08-01

申请人： UNITED MICROELECTRONICS CORP.

发明人： Pei-Jou Lee ,  Kun-Chen Ho ,  Hsuan-Hsu Chen ,  Chun-Lung Chen

IPC分类号： H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

摘要： A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate and a top electrode on the MTJ; forming a first inter-metal dielectric (IMD) layer around the MTJ and the top electrode; forming a stop layer on the first IMD layer; forming a second IMD layer on the stop layer; performing a first etching process to remove the second IMD layer and the stop layer; performing a second etching process to remove part of the top electrode; and forming a metal interconnection to connect to the top electrode.

公开(公告)号：US09793382B2

公开(公告)日：2017-10-17

申请号：US15470905

申请日：2017-03-28

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Lin Lu ,  Chun-Hsien Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC分类号： H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/26513 ,  H01L21/28525 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/41791 ,  H01L29/7848 ,  H01L29/785

摘要： A semiconductor device and a method of manufacturing the same, the semiconductor device includes a fin shaped structure, a gate structure, an epitaxial layer, a germanium layer, an interlayer dielectric layer and a first plug. The fin shaped structure is disposed on a substrate. The gate structure is formed across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure adjacent to the gate structure. The germanium layer is disposed on the epitaxial layer. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is disposed in the interlayer dielectric layer to contact the germanium layer.

公开(公告)号：US09673100B2

公开(公告)日：2017-06-06

申请号：US14536696

申请日：2014-11-10

申请人： UNITED MICROELECTRONICS CORP.

发明人： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chien-Ting Lin ,  Shih-Fang Tzou ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen

IPC分类号： H01L21/8234 ,  H01L21/311 ,  H01L29/06 ,  H01L27/088 ,  H01L29/49 ,  H01L21/768

CPC分类号： H01L21/823437 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/495 ,  H01L29/4966

摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a plurality of gate structures on the substrate; forming a first stop layer on the gate structures; forming a second stop layer on the first stop layer; forming a first dielectric layer on the second stop layer; forming a plurality of first openings in the first dielectric layer to expose the second stop layer; forming a plurality of second openings in the first dielectric layer and the second stop layer to expose the first stop layer; and removing part of the second stop layer and part of the first stop layer to expose the gate structures.

公开(公告)号：US20170084722A1

公开(公告)日：2017-03-23

申请号：US14919716

申请日：2015-10-21

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Wei-Hao Huang

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/66795 ,  H01L21/26513 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/7848 ,  H01L29/785

摘要： A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, agate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure, adjacent to the gate structure. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is formed in the interlayer dielectric layer, wherein the first plug is electrically connected to the epitaxial layer. The protection layer is disposed between the first plug and the gate structure.

公开(公告)号：US20160225662A1

公开(公告)日：2016-08-04

申请号：US14612235

申请日：2015-02-02

申请人： United Microelectronics Corp.

发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Feng-Yi Chang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Yi-Kuan Wu ,  Ying-Cheng Liu ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC分类号： H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/76816 ,  H01L21/76879

摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a dielectric layer on the ILD layer and the gate structure; forming an opening in the dielectric layer and the ILD layer; forming an organic dielectric layer (ODL) on the dielectric layer and in the opening; removing part of the ODL; removing part of the dielectric layer for extending the opening; removing the remaining ODL; and forming a contact plug in the opening.

摘要翻译： 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底和围绕栅极结构的层间电介质（ILD）层; 在ILD层和栅极结构上形成介电层; 在介电层和ILD层中形成开口; 在介质层和开口中形成有机介电层（ODL）; 去除部分ODL; 去除用于延伸开口的电介质层的一部分; 去除剩余的ODL; 并在开口中形成接触塞。

公开(公告)号：US09196699B1

公开(公告)日：2015-11-24

申请号：US14328720

申请日：2014-07-11

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Fu Hsu ,  Chun-Mao Chiou ,  Shih-Chieh Hsu ,  Jian-Cun Ke ,  Chun-Lung Chen ,  Lung-En Kuo

IPC分类号： H01L21/336 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66

CPC分类号： H01L29/495 ,  H01L21/28088 ,  H01L21/31116 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; depositing a liner on the gate structure and the substrate; and performing an etching process by injecting a gas comprising CH3F, O2, and He for forming a spacer adjacent to the gate structure.

摘要翻译： 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在基板上形成栅极结构; 在栅极结构和衬底上沉积衬垫; 并且通过注入包含CH 3 F，O 2和He的气体来进行蚀刻处理，以形成与栅极结构相邻的间隔物。