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公开(公告)号：US20140099751A1
公开(公告)日：2014-04-10
申请号：US13647344
申请日：2012-10-08
Applicant: UNITED MICROELECTRONICS CORP.
IPC: H01L21/336 , H01L31/18 , H01L21/28
CPC classification number: H01L31/1804 , H01L29/6659 , H01L29/7833 , Y02E10/547 , Y02P70/521
Abstract: The present invention provides a method of forming a doping region. A substrate is provided, and a poly-silicon layer is formed on the substrate. A silicon oxide layer is formed on the poly-silicon layer. An implant process is performed to form a doping region in the poly-silicon layer. The present invention further provides a method for forming a MOS.
Abstract translation: 本发明提供一种形成掺杂区域的方法。 提供基板，在基板上形成多晶硅层。 在多晶硅层上形成氧化硅层。 执行注入工艺以在多晶硅层中形成掺杂区域。 本发明还提供一种用于形成MOS的方法。
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公开(公告)号：US10276451B2
公开(公告)日：2019-04-30
申请号：US15679346
申请日：2017-08-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yong-Liang Li , Hao Su
IPC: H01L29/06 , H01L29/49 , H01L27/092 , H01L29/423 , H01L21/8238
Abstract: A semiconductor structure includes a substrate and a CMOS structure. The CMOS structure includes a PMOS structure and a NMOS structure. The PMOS structure includes two first source/drain regions disposed in the substrate, a first gate dielectric disposed partially in the substrate between the first source/drain regions, and a fully silicided gate electrode disposed on the first gate dielectric. The NMOS structure includes two second source/drain regions disposed in the substrate, a second gate dielectric disposed partially in the substrate between the second source/drain regions, and a non-silicided conductive gate electrode disposed on the second gate dielectric.
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Patent Agency Ranking
公开(公告)号：US20170316830A1
公开(公告)日：2017-11-02
申请号：US15638352
申请日：2017-06-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hao Su , Chow Yee Lim , CHAO JIANG , Hong Liao
IPC: G11C16/04 , H01L27/11521 , H01L23/528 , H01L23/522 , H01L21/28 , H01L29/51 , H01L21/268
CPC classification number: H01L23/5226 , G11C16/0433 , H01L21/2686 , H01L21/28273 , H01L23/528 , H01L27/11521 , H01L29/518
Abstract: A light-erasable embedded memory device and a method for manufacturing the same are provided in the present invention. The light-erasable embedded memory device includes a substrate with a memory region and a core circuit region, a floating gate on the memory region of the substrate, at least two light-absorbing films above the floating gate, wherein each light-absorbing film is provided with at least one dummy via hole overlapping the floating gate, and a dielectric layer on each light-absorbing film and filling up the dummy via holes.
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公开(公告)号：US10079204B2
公开(公告)日：2018-09-18
申请号：US15638352
申请日：2017-06-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hao Su , Chow Yee Lim , Chao Jiang , Hong Liao
IPC: H01L23/48 , H01L23/522 , H01L27/11521 , H01L29/51 , H01L21/28 , H01L21/268 , H01L23/528 , G11C16/04
CPC classification number: H01L23/5226 , G11C16/0433 , G11C16/18 , G11C17/143 , G11C2216/26 , H01L23/528 , H01L27/11521 , H01L27/11546 , H01L29/518
Abstract: A light-erasable embedded memory device and a method for manufacturing the same are provided in the present invention. The light-erasable embedded memory device includes a substrate with a memory region and a core circuit region, a floating gate on the memory region of the substrate, at least two light-absorbing films above the floating gate, wherein each light-absorbing film is provided with at least one dummy via hole overlapping the floating gate, and a dielectric layer on each light-absorbing film and filling up the dummy via holes.
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公开(公告)号：US09728260B1
公开(公告)日：2017-08-08
申请号：US15140506
申请日：2016-04-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hao Su , Chow Yee Lim , Chao Jiang , Hong Liao
IPC: H01L21/336 , G11C16/04 , H01L27/11521 , H01L29/51 , H01L21/28 , H01L21/268 , H01L23/528 , H01L23/522
CPC classification number: H01L23/5226 , G11C16/0433 , H01L21/2686 , H01L21/28273 , H01L23/528 , H01L27/11521 , H01L29/518
Abstract: A light-erasable embedded memory device and a method for manufacturing the same are provided in the present invention. The light-erasable embedded memory device includes a substrate with a memory region and a core circuit region, a floating gate on the memory region of the substrate, at least one light-absorbing film above the floating gate, wherein at least one light-absorbing film is provided with dummy via holes overlapping the floating gate, and a dielectric layer on the light-absorbing film and filling up the dummy via holes.
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公开(公告)号：US09209344B2
公开(公告)日：2015-12-08
申请号：US13647344
申请日：2012-10-08
Applicant: UNITED MICROELECTRONICS CORP.
CPC classification number: H01L31/1804 , H01L29/6659 , H01L29/7833 , Y02E10/547 , Y02P70/521
Abstract: The present invention provides a method of forming a doping region. A substrate is provided, and a poly-silicon layer is formed on the substrate. A silicon oxide layer is formed on the poly-silicon layer. An implant process is performed to form a doping region in the poly-silicon layer. The present invention further provides a method for forming a MOS.
Abstract translation: 本发明提供一种形成掺杂区域的方法。 提供基板，在基板上形成多晶硅层。 在多晶硅层上形成氧化硅层。 执行注入工艺以在多晶硅层中形成掺杂区域。 本发明还提供一种用于形成MOS的方法。
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公开(公告)号：US10475708B2
公开(公告)日：2019-11-12
申请号：US16299395
申请日：2019-03-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yong-Liang Li , Hao Su
IPC: H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/49
Abstract: A semiconductor structure includes a substrate and a CMOS structure. The CMOS structure includes a PMOS structure and a NMOS structure. The PMOS structure includes two first source/drain regions disposed in the substrate, a first gate dielectric disposed partially in the substrate between the first source/drain regions, and a fully silicided gate electrode disposed on the first gate dielectric. The NMOS structure includes two second source/drain regions disposed in the substrate, a second gate dielectric disposed partially in the substrate between the second source/drain regions, and a non-silicided conductive gate electrode disposed on the second gate dielectric.
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