公开(公告)号：US20230025163A1

公开(公告)日：2023-01-26

申请号：US17404939

申请日：2021-08-17

Applicant: United Microelectronics Corp.

Inventor： Wen Wen Gong ,  Xiaofei Han ,  Chow Yee Lim ,  Hong Liao ,  Jun Qian

IPC: H01L21/308 ,  H01L27/11556

Abstract: A method of manufacturing a semiconductor structure including the following steps is provided. A substrate is provided. The substrate has a first region and a second region. A stacked structure is formed on the substrate in the first region. The stacked structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, a first conductive layer, and a first hard mask layer. A dielectric material layer is formed on the substrate in the second region. A second conductive layer is formed on the dielectric material layer in the second region. A first patterned photoresist layer is formed. The first hard mask layer exposed by the first patterned photoresist layer and a portion of the dielectric material layer exposed by the first patterned photoresist layer are removed by using the first patterned photoresist layer as a mask.

公开(公告)号：US09911847B1

公开(公告)日：2018-03-06

申请号：US15647286

申请日：2017-07-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hock Chun Chin ,  Lanxiang Wang ,  Hong Liao ,  Chao Jiang ,  Chow Yee Lim

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/78391 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28291 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/7881 ,  H01L29/792

Abstract: A non-volatile memory device includes a substrate, a gate stack structure, an erase gate structure, and a ferroelectric layer. The gate stack structure is disposed on the substrate. The erase gate structure is disposed on the substrate and disposed at a first side of the gate stack structure. The ferroelectric layer is disposed on a sidewall of the gate stack structure, and the ferroelectric layer is disposed between the gate stack structure and the erase gate structure. The ferroelectric layer disposed between the gate stack structure and the erase gate structure may be used to forma negative capacitance effect for amplifying the voltage applied to the erase gate structure. The purpose of reducing power consumption may be achieved accordingly.

公开(公告)号：US09859290B1

公开(公告)日：2018-01-02

申请号：US15342098

申请日：2016-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lanxiang Wang ,  Hong Liao ,  Chao Jiang ,  Bo Liu ,  Xin Xu

IPC: H01L21/336 ,  H01L27/11521 ,  H01L29/49 ,  H01L29/423 ,  H01L23/522 ,  H01L27/08 ,  H01L29/92 ,  H01L27/108 ,  H01L27/11502

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L23/485 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/10852 ,  H01L27/11502 ,  H01L28/55 ,  H01L29/42324 ,  H01L29/4966 ,  H01L29/92 ,  H01L2924/30105

Abstract: A method for fabricating memory device includes the steps of: providing a substrate; forming a tunnel oxide layer on the substrate; forming a first gate layer on the tunnel oxide layer; forming a negative capacitance (NC) insulating layer on the first gate layer; and forming a second gate layer on the NC insulating layer. Preferably, the second gate layer further includes a work function metal layer on the NC insulating layer and a low resistance metal layer on the work function metal layer.

公开(公告)号：US20170316830A1

公开(公告)日：2017-11-02

申请号：US15638352

申请日：2017-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao Su ,  Chow Yee Lim ,  CHAO JIANG ,  Hong Liao

IPC: G11C16/04 ,  H01L27/11521 ,  H01L23/528 ,  H01L23/522 ,  H01L21/28 ,  H01L29/51 ,  H01L21/268

CPC classification number: H01L23/5226 ,  G11C16/0433 ,  H01L21/2686 ,  H01L21/28273 ,  H01L23/528 ,  H01L27/11521 ,  H01L29/518

Abstract: A light-erasable embedded memory device and a method for manufacturing the same are provided in the present invention. The light-erasable embedded memory device includes a substrate with a memory region and a core circuit region, a floating gate on the memory region of the substrate, at least two light-absorbing films above the floating gate, wherein each light-absorbing film is provided with at least one dummy via hole overlapping the floating gate, and a dielectric layer on each light-absorbing film and filling up the dummy via holes.

公开(公告)号：US20170213854A1

公开(公告)日：2017-07-27

申请号：US15006123

申请日：2016-01-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： LANXIANG WANG ,  Hong Liao ,  CHAO JIANG

IPC: H01L27/12 ,  H01L21/77 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L21/77 ,  H01L27/1218 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78603 ,  H01L2021/775

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a gate layer on the substrate; forming a first gate dielectric layer on the gate layer; forming a first channel layer on the first region and a second channel layer on the second region; and forming a first source/drain on the first channel layer and a second source/drain on the second channel layer.

公开(公告)号：US09331200B1

公开(公告)日：2016-05-03

申请号：US14590008

申请日：2015-01-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lanxiang Wang ,  Hong Liao ,  Chao Jiang ,  Duan Quan Liao ,  Ye Chao Li

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/161 ,  H01L29/45

CPC classification number: H01L29/7848 ,  H01L29/161 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66568 ,  H01L29/66636

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; and forming a first epitaxial layer, a second epitaxial layer, and a silicide layer in the substrate adjacent to the gate structure. Preferably, the first epitaxial layer, the second epitaxial layer, and the silicide layer comprise SiGeSn.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底; 以及在与栅极结构相邻的衬底中形成第一外延层，第二外延层和硅化物层。 优选地，第一外延层，第二外延层和硅化物层包括SiGeSn。

公开(公告)号：US09922832B1

公开(公告)日：2018-03-20

申请号：US15628753

申请日：2017-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xiao-Fei Han ,  Ju-Bao Zhang ,  Chao Jiang ,  Hong Liao ,  Wen-Wen Gong

IPC: H01L21/28 ,  H01L29/66

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L27/11548 ,  H01L29/66825

Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method of the semiconductor structure includes the following steps: providing a semiconductor substrate, wherein the semiconductor substrate has a first region and a second region surrounding the first region; forming a gate stack and a dummy gate stack in the first region, wherein the dummy gate stack surrounds the gate stack; forming an oxide layer on an exterior wall and a top surface of the dummy gate stack; forming a dummy conductive layer on the gate stack, the dummy gate stack and the oxide layer, wherein the dummy conductive layer has a concave bowl-shaped top surface in the first region; and performing a chemical mechanical polishing (CMP) process on the dummy conductive layer.

公开(公告)号：US20150303120A1

公开(公告)日：2015-10-22

申请号：US14256989

申请日：2014-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jubao Zhang ,  Xing Hua Zhang ,  Hong Liao

IPC: H01L21/66 ,  H01L23/522 ,  H01L21/78 ,  H01L23/00

Abstract: A method for fabricating semiconductor package structure is disclosed. The method includes: providing a wafer having a front side and a backside; forming a plurality of through-silicon vias (TSVs) in the wafer and a plurality of metal interconnections on the TSVs, in which the metal interconnections are exposed from the front side of the wafer; performing a monitoring step to screen for TSV failures from the backside of the wafer; and bonding the wafer to a substrate.

Abstract translation: 公开了半导体封装结构的制造方法。 该方法包括：提供具有正面和背面的晶片; 在晶片中形成多个通硅通孔（TSV）和在TSV上的多个金属互连，其中金属互连从晶片的前侧露出; 执行监视步骤以从晶片的背面屏蔽TSV故障; 并将晶片接合到基板。

公开(公告)号：US20140099751A1

公开(公告)日：2014-04-10

申请号：US13647344

申请日：2012-10-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao Su ,  Hang Hu ,  Hong Liao

IPC: H01L21/336 ,  H01L31/18 ,  H01L21/28

CPC classification number: H01L31/1804 ,  H01L29/6659 ,  H01L29/7833 ,  Y02E10/547 ,  Y02P70/521

Abstract: The present invention provides a method of forming a doping region. A substrate is provided, and a poly-silicon layer is formed on the substrate. A silicon oxide layer is formed on the poly-silicon layer. An implant process is performed to form a doping region in the poly-silicon layer. The present invention further provides a method for forming a MOS.

Abstract translation: 本发明提供一种形成掺杂区域的方法。 提供基板，在基板上形成多晶硅层。 在多晶硅层上形成氧化硅层。 执行注入工艺以在多晶硅层中形成掺杂区域。 本发明还提供一种用于形成MOS的方法。

公开(公告)号：US10147806B1

公开(公告)日：2018-12-04

申请号：US15602114

申请日：2017-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bin Tang ,  Jubao Zhang ,  Xiaofei Han ,  Chao Jiang ,  Hong Liao

IPC: H01L21/283 ,  H01L21/762 ,  H01L27/11531 ,  H01L29/788 ,  H01L29/66 ,  H01L27/11521 ,  H01L21/8234

Abstract: A method of fabricating a floating gate includes providing a substrate divided into a cell region and a logic region. A silicon oxide layer and a silicon nitride layer cover the cell region and the logic region. Numerous STIs are formed in the silicon nitride layer, the silicon oxide layer, and the substrate. Later, the silicon nitride layer within the cell region is removed to form one recess between the adjacent STIs within the cell region while the silicon nitride layer within the logic region remains. Subsequently, a conductive layer is formed to fill the recess. The conductive layer is thinned to form a floating gate.