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公开(公告)号：US11757016B2
公开(公告)日：2023-09-12
申请号：US17709385
申请日：2022-03-30
发明人： Yi-Fan Li , Wen-Yen Huang , Shih-Min Chou , Zhen Wu , Nien-Ting Ho , Chih-Chiang Wu , Ti-Bin Chen
IPC分类号： H01L29/49 , H01L29/40 , H01L27/092
CPC分类号： H01L29/4966 , H01L27/092 , H01L29/401
摘要： A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.
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公开(公告)号：US20220223710A1
公开(公告)日：2022-07-14
申请号：US17709385
申请日：2022-03-30
发明人： Yi-Fan Li , Wen-Yen Huang , Shih-Min Chou , Zhen Wu , Nien-Ting Ho , Chih-Chiang Wu , Ti-Bin Chen
IPC分类号： H01L29/49 , H01L29/40 , H01L27/092
摘要： A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.
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公开(公告)号：US09659937B2
公开(公告)日：2017-05-23
申请号：US14683128
申请日：2015-04-09
发明人： Ching-Yun Chang , Chi-Mao Hsu , Wei-Ming Hsiao , Nien-Ting Ho , Kuo-Chih Lai
IPC分类号： H01L27/092 , H01L29/49 , H01L21/28 , H01L21/8234
CPC分类号： H01L27/0922 , H01L21/28088 , H01L21/82345 , H01L21/823842 , H01L27/092 , H01L29/4966 , H01L29/66545
摘要： A semiconductor process of forming metal gates with different threshold voltages includes the following steps. A substrate having a first area and a second area is provided. A dielectric layer and a first work function layer are sequentially formed on the substrate of the first area and the second area. A second work function layer is directly formed on the first work function layer of the first area. A third work function layer is directly formed on the first work function layer of the second area, where the third work function layer is different from the second work function layer. The present invention also provides a semiconductor structure formed by said semiconductor process.
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公开(公告)号：US09653300B2
公开(公告)日：2017-05-16
申请号：US13864218
申请日：2013-04-16
发明人： Nien-Ting Ho , Chien-Hao Chen , Hsin-Fu Huang , Chi-Yuan Sun , Wei-Yu Chen , Min-Chuan Tsai , Tsun-Min Cheng , Chi-Mao Hsu
IPC分类号： H01L27/148 , H01L21/28 , H01L29/49 , H01L21/8238 , H01L29/51 , H01L29/66 , H01L29/78 , H01L29/165
CPC分类号： H01L21/28088 , H01L21/823842 , H01L29/165 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7843 , H01L29/7848
摘要： A manufacturing method of a metal gate structure is provided. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. Finally, the gate trench is filled up with a conductive metal layer.
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公开(公告)号：US09331161B1
公开(公告)日：2016-05-03
申请号：US14554068
申请日：2014-11-26
发明人： Chi-Ju Lee , Yao-Chang Wang , Nien-Ting Ho , Chi-Mao Hsu , Kuan-Cheng Su , Main-Gwo Chen , Hsiao-Kwang Yang , Fang-Hong Yao , Sheng-Huei Dai , Tzung-Lin Li
IPC分类号： H01L21/02 , H01L29/423 , H01L29/49 , H01L29/51 , H01L21/28
CPC分类号： H01L29/42376 , H01L21/02178 , H01L21/02186 , H01L21/02194 , H01L21/02244 , H01L21/02255 , H01L21/28079 , H01L21/28088 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659 , H01L29/78
摘要： The present invention provides a metal gate structure which is formed in a trench of a dielectric layer. The metal gate structure includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench and comprises a bottom portion and a side portion, wherein a ratio between a thickness of the bottom portion and a thickness of the side portion is between 2 and 5. The trench is filled with the metal layer. The present invention further provides a method of forming the metal gate structure.
摘要翻译： 本发明提供了形成在电介质层的沟槽中的金属栅极结构。 金属栅极结构包括功函数金属层和金属层。 工作功能金属层设置在沟槽中，并且包括底部和侧部，其中底部的厚度和侧部的厚度之间的比率在2-5之间。沟槽填充有金属 层。 本发明还提供一种形成金属栅极结构的方法。
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公开(公告)号：US20230369442A1
公开(公告)日：2023-11-16
申请号：US18226264
申请日：2023-07-26
发明人： Yi-Fan Li , Wen-Yen Huang , Shih-Min Chou , Zhen Wu , Nien-Ting Ho , Chih- Chiang Wu , Ti-Bin Chen
IPC分类号： H01L29/49 , H01L29/40 , H01L27/092
CPC分类号： H01L29/4966 , H01L27/092 , H01L29/401
摘要： A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.
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公开(公告)号：US20230369441A1
公开(公告)日：2023-11-16
申请号：US18226262
申请日：2023-07-26
发明人： Yi-Fan Li , Wen-Yen Huang , Shih-Min Chou , Zhen Wu , Nien-Ting Ho , Chih-Chiang Wu , Ti-Bin Chen
IPC分类号： H01L29/49 , H01L27/092 , H01L29/40
CPC分类号： H01L29/4966 , H01L27/092 , H01L29/401
摘要： A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.
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公开(公告)号：US11139384B2
公开(公告)日：2021-10-05
申请号：US16561002
申请日：2019-09-04
发明人： Kuo-Chih Lai , Yun-Tzu Chang , Wei-Ming Hsiao , Nien-Ting Ho , Shih-Min Chou , Yang-Ju Lu , Ching-Yun Chang , Yen-Chen Chen , Kuan-Chun Lin , Chi-Mao Hsu
摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.
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公开(公告)号：US20200006514A1
公开(公告)日：2020-01-02
申请号：US16561002
申请日：2019-09-04
发明人： Kuo-Chih Lai , Yun-Tzu Chang , Wei-Ming Hsiao , Nien-Ting Ho , Shih-Min Chou , Yang-Ju Lu , Ching-Yun Chang , Yen-Chen Chen , Kuan-Chun Lin , Chi-Mao Hsu
摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.
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公开(公告)号：US10199228B2
公开(公告)日：2019-02-05
申请号：US15479292
申请日：2017-04-05
发明人： Nien-Ting Ho , Chien-Hao Chen , Hsin-Fu Huang , Chi-Yuan Sun , Wei-Yu Chen , Min-Chuan Tsai , Tsun-Min Cheng , Chi-Mao Hsu
IPC分类号： H01L21/76 , H01L21/28 , H01L29/49 , H01L21/8238 , H01L29/51 , H01L29/66 , H01L29/78 , H01L29/165
摘要： A manufacturing method of a metal gate structure includes the following steps. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. The silicon-containing work function layer includes a vertical portion and a horizontal portion. Finally, the gate trench is filled up with a conductive metal layer.
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